发表机构
Technical University of Munich; Remote Sensing Technology Institute, German Aerospace Center (DLR); University of the Bundeswehr Munich（慕尼黑工业大学; 德国航空航天中心遥感技术研究所; 慕尼黑联邦国防军大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本研究在ZCU102 FPGA平台部署联合SAR去噪与数据压缩框架，发现ReLU比GDN更适配SAR图像、残差块增益低且FPGA能效最高，为星载SAR压缩提供部署方案。
AI 中文摘要
下一代合成孔径雷达（SAR）任务产生的数据传输速度远超下行链路能力，因此星上数据压缩对于近实时地球观测至关重要。学习型图像压缩（LIC）相比当前业务中使用的手工编解码器具有更优的率失真性能，近期研究表明，同时对SAR图像进行去噪和压缩可提升表征能力并实现更高压缩率。然而，这些方法尚未满足星载系统严格的功耗、计算和运行约束。本研究通过在基于嵌入式ZCU102 FPGA的平台上部署联合SAR去噪与数据压缩（DDC）框架，引入适配加速器定点算术及有限支持操作的模型改进，以填补这一空白。我们在不同精度级别及CPU、GPU、FPGA平台上评估了四种模型拓扑，得到多项对设计有直接指导意义的发现：将传统GDN激活函数替换为普通ReLU可提升SAR图像质量，说明自然图像压缩的设计原则不一定适用于SAR图像；残差块在计算量增加10倍的情况下几乎无表征增益；FPGA是测试平台中能效最高的。这些结果共同构建了可用的边缘部署工作流，为星载SAR压缩提供了基于证据的起点，代码可在指定URL获取。
英文摘要
Next-generation Synthetic Aperture Radar (SAR) missions will generate data far faster than they can downlink, making onboard data reduction essential for near-real-time Earth observation. Learned Image Compression (LIC) offers better rate-distortion performance than handcrafted codecs used operationally today, and recent work shows that simultaneously despeckling and compressing SAR imagery enables better representation capacity while unlocking higher compression rates. These methods, however, have yet to be confronted with the strict power, compute, and operational constraints of spaceborne systems. In this work, we bridge this gap by deploying a joint SAR Despeckling and Data Compression (DDC) framework on an embedded ZCU102 FPGA-based platform, introducing model adaptations that respect the accelerator's fixed-point arithmetic and limited set of supported operations. We evaluate four model topologies across precision levels and across CPU, GPU, and FPGA platforms, revealing several findings with direct design implications. We find that replacing conventional GDN activation functions with plain ReLU improves quality on SAR, suggesting that design principles established for compression of natural images do not necessarily transfer to SAR imagery. In addition, we demonstrate that residual blocks offer little representational benefit for ten times the compute, and show that the FPGA is the most energy-efficient of the platforms tested. Together, these results set a functioning edge deployment workflow and an evidence-based starting point for onboard SAR compression. The code is available at https://github.com/CedricLeon/SAR_DDC_FPGA.
CommentsSubmitted to IEEE Transactions on Geoscience and Remote Sensing (TGRS). 11 pages, 8 figures, 4 tables
