AI 中文总结
该研究设计一款高增益低噪声前置放大器板，采用三级架构，在LGAD、PIN、3D硅探测器测试中性能优异，优于参考设计，还开发了六通道变体，为4D追踪探测器表征及ASIC开发奠定基础。
AI 中文摘要
我们提出一款为读出低电荷半导体探测器设计的高增益、低噪声前置放大器板，该探测器具体为高能量物理应用中的低增益雪崩探测器（LGAD）和三维（3D）硅传感器。该电路采用三级架构，前端为基于分立SiGe:C双极结型晶体管（BJT）的跨阻放大器（TIA），后续两级为采用LTC6431芯片的电阻反馈放大级。该配置实现了115.27 mV ns/fC的电荷增益，在0.5 fC至25 fC的输入范围内具有优异线性度，带宽覆盖34.0 MHz至594.3 MHz。结合LGAD探测器的实验评估显示，在20 °C下时间分辨率为36.41 ps，等效噪声电荷（ENC）为0.18 fC；此外，对无增益层的传统PIN传感器测试得到时间分辨率76.10 ps、ENC为0.10 fC，对3D硅传感器测试得到时间分辨率39.40 ps、ENC为0.09 fC，所有测试均在相同热条件下进行。所有配置均证实该板在低信号场景下的能力，显著优于以往参考设计。还开发了该板的六通道变体以支持位置敏感测量。这些结果表明该板适用于实验室4D追踪探测器表征，同时为专用ASIC开发奠定基础。
英文摘要
We present a high-gain, low-noise preamplifier board designed for reading out low-charge semiconductor detectors--specifically Low-Gain Avalanche Detectors (LGADs) and three-dimensional (3D) silicon sensors--in high-energy physics applications. The circuit employs a three-stage architecture featuring a discrete SiGe:C bipolar junction transistor (BJT)-based transimpedance amplifier (TIA) front-end followed by two resistive feedback amplification stages using LTC6431 chips. This configuration achieves a charge gain of 115.27 mV ns/fC with excellent linearity over an input range of 0.5 fC to 25 fC and a wide bandwidth spanning from 34.0 MHz to 594.3 MHz. Experimental evaluations coupled with LGAD detectors demonstrate a time resolution of 36.41 ps and an equivalent noise charge (ENC) of 0.18 fC at 20 °C. Furthermore, tests with conventional PIN sensors without a gain layer yield a timing resolution of 76.10 ps with an ENC of 0.10 fC, and tests with the 3D silicon detector yield 39.40 ps with an ENC of 0.09 fC, all measured under the same thermal condition. All configurations confirm the board's capability in low-signal regimes, significantly outperforming previous reference designs. A six-channel variant of the board has also been developed to support position-sensitive measurements. These findings demonstrate the board's suitability for laboratory-based 4D tracking detector characterisation, while simultaneously providing the groundwork for dedicated ASIC development.
