用于性能-安全权衡的混合ASIC-FPAA架构
Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
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中文总结 AI 辅助
本文提出结合ASIC与FPAA的混合架构，通过可编程TP、虚拟TP等技术混淆模拟电路拓扑，在Δ-Σ调制器上实现安全性能提升5倍且性能损失极小，解决了模拟电路的性能-安全权衡问题。
中文摘要 AI 辅助
本文提出一种结合专用集成电路（ASIC）与现场可编程模拟阵列（FPAA）的混合架构，以解决模拟电路中的性能-安全权衡问题。研究开发了一种可编程晶体管对（TP），该器件可在多对晶体管组成的阵列中混淆模拟电路的拓扑结构，同时最大限度降低安全特性带来的电路性能下降。此外，还提出了一种利用虚拟晶体管对的技术，该技术通过混淆构成目标模拟电路的有源晶体管数量，进一步掩盖电路的拓扑结构；同时还开发了一种可混淆模拟电路整体拓扑结构的方法。FPAA可通过将整个电路拓扑结构编程到晶体管对阵列上，提供最高级别的安全鲁棒性，但会牺牲性能。对于需要多个可配置模拟模块（CAB）的大型模拟电路，研究开发了一种算法，该算法在考虑性能与安全权衡的前提下，识别并映射电路中最适合在FPAA架构上进行混淆的子模块。以Δ-Σ调制器为例，研究选择比较器模块在FPAA架构上实现，与未混淆的Δ-Σ调制器相比，该实现的有效位数（ENOB）减少不足0.25%，功耗增加28.1%。研究针对最新攻击方法评估了所提技术的安全鲁棒性，结果显示，采用所提技术后，通过开发的度量标准衡量，安全性能提升了5倍，且未损害性能。
英文摘要
In this paper, a hybrid architecture that combines an application specific integrated circuit (ASIC) and a field-programmable analog array (ASIC-FPAA) is proposed to address the performance-security trade-off in analog circuits. A programmable transistor pair (TP) is developed that obfuscates the topology of an analog circuit within an array of transistor pairs while minimizing the degradation in circuit performance due to the implemented security features. In addition, a technique that utilizes dummy transistor pairs is proposed that further masks the topology of a circuit by obfuscating the number of active transistors that comprise the target analog circuit. A method to obfuscate the entire topology of an analog circuit is also developed. The FPAA provides the highest-level of security robustness as the entire circuit topology is programmed onto the transistor pair array, while trading-off performance. For large analog circuits requiring multiple configurable analog blocks (CABs), an algorithm is developed that identifies and maps the sub-blocks of the circuit best suited for obfuscation on the FPAA fabric, while accounting for the trade-off between performance and security. For the delta-sigma modulator, the comparator module is selected for implementation on the FPAA fabric, which results in a reduction of less than 0.25% in the effective number of bits (ENOB) and an increase of 28.1% in the power consumption as compared to an unobfuscated delta-sigma modulator. The security robustness of the proposed techniques are evaluated against the latest attack methodologies. Results indicate that the proposed techniques provide a 5x improvement in security as measured by a developed metric without compromising performance.
