用于频率合成器的可编程斜坡发生器的设计与分析
Design and Analysis of a Programmable Ramp Generator for Frequency Synthesizers
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中文总结 AI 辅助
该研究设计了用于频率合成器的全数字可编程斜坡发生器，分析了其三类电路级约束并提出系统化设计算法，实现的16位PRG经多轮廓验证及FPGA原型测试可实时运行。
中文摘要 AI 辅助
本文提出了一种全数字可编程斜坡发生器（PRG），用于频率调制连续波雷达、扩频时钟生成以及测试与测量应用中的可重构频率斜坡合成器。该研究提出了一种新颖的模块化架构，集成了基于相位累加器的频率扫描发生器和驱动多模分频器（MMD）的Δ-Σ调制器（DSM），可对斜坡斜率、带宽和持续时间进行独立数字控制。现有研究虽已实现啁啾合成，但尚未联合分析PRG可靠运行的电路级约束。本研究确定并分析了三类此类约束：（a）动态更新下的MMD八度边界行为；（b）分频器同步时序；（c）DSM对步长持续时间和可实现斜率的限制。这些约束共同定义了PRG的设计空间，支持将应用级规格直接映射到硬件参数的系统化算法。遵循该方法，在台积电65纳米CMOS工艺中实现的16位PRG已通过18种斜坡轮廓验证，且在赛灵思 Spartan-7 FPGA上的硬件原型证实其可实时运行。
英文摘要
This paper presents a fully digital Programmable Ramp Generator (PRG) for reconfigurable frequency-ramp synthesizers used in Frequency-Modulated Continuous-Wave radar, spread-spectrum clock generation, and test and measurement applications. A novel modular architecture is proposed, integrating a phase-accumulator-based frequency sweep generator and Delta-Sigma Modulator (DSM) that drives a Multi-Modulus Divider (MMD), giving independent digital control over ramp slope, bandwidth, and duration. While prior works demonstrate chirp synthesis, the circuit-level constraints governing reliable PRG operation have not been jointly analyzed. This work identifies and analyzes three such constraints: (a) MMD octave-boundary behavior under dynamic updates, (b) divider-synchronous timing, and (c) DSM limits on step duration and achievable slope. Together, these constraints define the PRG design space, enabling a systematic algorithm that maps application-level specifications directly to hardware parameters. Following this methodology, a 16-bit PRG implemented in TSMC 65 nm CMOS is verified across 18 ramp profiles and hardware prototyping on a Xilinx Spartan-7 FPGA confirms real-time operation.
