发表机构
QuEra Computing Inc.; University of Chicago; Virginia Tech（QuEra 计算公司; 芝加哥大学; 弗吉尼亚理工大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
提出GALA定制码，构造出多款硬件兼容的速率1/2量子纠错码，其中部分码的逻辑错误率低、周期短，性能优于此前同类码。
AI 中文摘要
可重构中性原子阵列上的高速率量子低密度奇偶校验码可降低量子纠错的开销，但近期器件仅支持数百个量子比特，且受限于少数交叉声光偏转器（AOD）的可重构性。实用的码除低开销外还需紧凑，校验与逻辑门需映射为硬件兼容的物理指令。本文提出GALA码，即带主动正交性的群作用提升码，其在乘积群G=Hₖ×Cₘ（或Hₖ⋉Cₘᵏ）上提升。小型非阿贝尔因子Hₖ提供主动正交性，达到1/2速率且具有高重量距离；大型阿贝尔因子Cₘ提供对称性，赋予码自同构及明确简单的AOD移动调度。由此，硬件兼容性与逻辑能力成为码搜索的可定制输入，而非事后验证的属性，使GALA定制码从构造上满足要求。GALA家族包含文献[arXiv:2601.08824, arXiv:2604.16209]中多个已发现的速率1/2 Kasai码，同时给出更简洁的参数界、逻辑操作及带AOD兼容折叠横向克利福德门的ZX对偶变体。本次搜索得到紧凑自对偶码[[132, 30, 12]]，其4环数量少（几乎 girth-6），在10⁻³物理错误率下存储的逻辑错误率（LER）低于10⁻⁸，症候提取周期为3.1ms，具备横向克利福德门；还有girth-6、速率1/2的[[672, 336, 12]]，周期6.76ms，外推LER低于10⁻¹⁰；以及打破速率1/2壁垒的[[1752, 880, 14]]和[[2232, 1120, 16]]，其经严格验证的距离大于校验重量，且均小于此前已知的硬件兼容速率1/2码。
英文摘要
Achieving useful fault-tolerant applications requires co-designing the quantum error-correcting code for footprint, logical instruction set, and hardware compatibility simultaneously. Recent breakthroughs in ultra-high-rate codes have the potential to reduce footprint of large scale quantum applications but their practical utility is limited without an addressable logical instruction set and efficient implementation on near term hardware. Reconfigurable neutral atom arrays, for example, support only hundreds of qubits with constrained reconfigurability from a few crossed acousto-optic deflectors (AOD). We introduce the GALA codes, or Group-Action Lifts with Active orthogonality, that allows such co-design by construction. GALA lifts over a product group $G = H_k \times C_m$ (or $H_k \ltimes C_m^k$); the small non-abelian factor $H_k$ supplies active orthogonality that improves qubit overhead, reaching 1/2 encoding rate with above-weight distance, while the large abelian factor $C_m$ supplies symmetries that give code automorphisms and explicit, simple AOD move schedules. Logical addressibility and hardware compatibility follow directly from construction, rather than verified post-hoc. The GALA family contains several known rate-1/2 Kasai codes of Ref.[arXiv:2601.08824, arXiv:2604.16209] while exposing simpler parameter bounds, logical operations, and ZX-dual variants with AOD-compatible fold-transversal Clifford gates. In particular, we find a compact self-dual $[[132,30,12]]$ with $1.0^{+0.9}_{-0.6}\times 10^{-9}$ per-round per-qubit logical error rate at $10^{-3}$ physical error rate, equipped with 3.1 ms syndrome-extraction cycles and an addressable logical instruction set; a ZX-dual, girth-6, rate-1/2 $[[672,336,12]]$ with a 6.76 ms cycles; and barrier-breaking $[[1752,880,14]]$ and $[[2232,1120,16]]$ smaller than previously known hardware-compatible rate-1/2 codes.
