AI 中文总结
该研究针对量子控制系统的内存瓶颈，提出集成DRAM与BRAM的Ant-Q设计，经26个电路验证可大幅降低开销，目前正集成至QubiC 3.0。
AI 中文摘要
随着量子计算持续展现出潜力并吸引越来越多的关注，为推动量子器件发展，人们对更精确的实验需求不断增长；同时，为验证更多领域应用，对更高的电路吞吐量需求也在提升。然而，量子控制系统层存在内存瓶颈，其源于片上BRAM容量有限以及DRAM的非确定性延迟。为突破该瓶颈，本文提出Ant-Q，一种将DRAM与BRAM集成的内存层次结构设计，支持流水线式量子电路执行，同时确保电路间时序的确定性。我们使用26个真实世界的实验及计算电路对Ant-Q进行评估，结果显示Ant-Q支持1Q和2Q随机基准测试的深度电路，并将电路加载与读出上行链路相对于执行时间的开销从22.90%-1417.05%降至接近零。Ant-Q正被集成到QubiC 3.0中，部分功能已可用。
英文摘要
As quantum computing continues to demonstrate promise and attract growing attention, there is an increasing need for more precise experiments to advance the development of quantum devices, as well as higher circuit throughput to validate more domain applications. However, this need is hindered by a memory bottleneck at the quantum control system layer, arising from limited on-chip BRAM capacity and the non-deterministic latency of DRAM. To break this bottleneck, we present Ant-Q, a memory hierarchy design that integrates DRAM with BRAM to support pipelined quantum circuit execution while ensuring deterministic inter-circuit timing. We evaluated Ant-Q using 26 real-world experimental and computing circuits. The results show that Ant-Q supports deep circuits for 1Q and 2Q Randomized Benchmarking and reduces the overhead of circuit loading and readout uplink relative to execution time from 22.90%-1417.05% to near zero. Ant-Q is being integrated into QubiC 3.0, with part of its functionalities already available.
