AI 中文总结
该研究针对对称量子电路路由的不均衡问题，通过分析拓扑约束提出均衡分配方法，可显著减少对称破坏，为量子编译器优化和芯片设计提供了对称性感知的目标方向。
AI 中文摘要
将量子程序映射到受限物理芯片需要SWAP（交换）操作，会带来深度和误差代价。在对称程序中，这种路由开销会破坏理论对称性，因为相同的逻辑角色会经历不均等的洗牌。虽然这通常被归因于硬件拓扑，但研究表明这是一个两级现象：量子比特块的形状决定了它是否能承载均衡分配；当均衡成为可能时，实际的不均衡由逻辑到物理的分配决定，意味着均衡分配可以完美均匀地分配路由成本，且无需额外深度。通过对57量子比特的"heavy-hex"（重六角）晶格进行穷举搜索，研究人员证明了这些拓扑约束：对于四部分环，124个连通块中有108个可实现无成本均衡分配，16个例外为星形；对于六部分环，紧凑块无法实现无成本均衡；对于完全连接的四部分对称性，均衡在任何深度都结构上不可能。使用实际误差率的模拟显示，相对于最坏情况的集中分配，均衡分配使原始度量的对称破坏减少92.7%（95%置信区间[+89.8%, +95.3%]），退相干校正度量的对称破坏减少87.0%（95%置信区间[+79.6%, +94.1%]），p值为2.45×10^-32；衬底误差异质性对该效应的贡献最多为10.8%。值得注意的是，切换到编译器最高通用优化级别并未使路由不均衡产生统计显著变化，凸显了针对性的感知对称性编译 passes（ passes 指编译过程中的处理步骤）的必要性。当块几何允许时，路由不均衡是编译器选择而非硬件限制，因此感知对称性分配应成为编译器优化和芯片设计的主要目标。
英文摘要
Mapping quantum programs to restricted physical chips requires SWAP operations, incurring depth and error penalties. In symmetric programs, this routing overhead breaks theoretical symmetry because identical logical roles experience unequal shuffling. While often attributed to hardware topology alone, we show this is a two-level phenomenon. A qubit patch's shape dictates if it can host a balanced assignment. When balance is possible, the actual imbalance is set by the logical-to-physical assignment, meaning a balanced assignment can distribute routing costs perfectly evenly at no extra depth. Through exhaustive search on a 57-qubit "heavy-hex" lattice, we prove these topological constraints. For a four-part ring, 108 of 124 connected patches admit a cost-free balanced assignment, with the 16 exceptions being star-shaped. For a six-part ring, cost-free balance is impossible on compact patches. For a fully connected four-part symmetry, balance is structurally impossible at any depth. Simulations using realistic error rates show that, relative to the worst-case concentrated assignment, balanced assignments reduce symmetry-breaking by 92.7% (95% CI [+89.8%, +95.3%]) for the raw metric and 87.0% (95% CI [+79.6%, +94.1%]) for the decoherence-corrected measure (p = 2.45 x 10^-32). Substrate error heterogeneity accounts for at most 10.8% of this effect. Notably, switching to the compiler's highest generic optimization level did not yield a statistically significant change in routing imbalance, highlighting the need for targeted symmetry-aware passes. When patch geometry permits, routing imbalance is a compiler choice rather than a hardware limitation. Thus, symmetry-aware assignment should be a primary objective for compiler optimization and chip design.
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