AI 中文总结
该研究提出零量子比特开销的全局控制量子纠错架构，利用循环稳定子码结合全局iSWAP门和单量子比特门，大幅提升QEC阈值，且阈值随局域测量位点增加而优化，实现布线与容错的权衡。
AI 中文摘要
实现容错能力意味着量子比特数量需提升数个数量级，而传统超导架构若不解决所谓“布线问题”便无法维持这一规模。全局控制可规避该瓶颈，但在先前提出的全局架构上实施量子纠错（QEC）会产生极高的开销，原因在于全局设备中用于计算和辅助的量子比特需分别执行纠错程序。我们通过引入首个零量子比特开销的全局控制架构解决了这一问题：每个物理量子比特均为计算量子比特，因此所有量子比特均受单一纠错方案保护。我们确定了一类可通过全局iSWAP门和单量子比特门实现的循环稳定子码，其QEC阈值比先前全局控制阵列的估计值大近七个数量级。我们进一步表明，随着全局架构增加有限数量的局域测量位点，这些阈值会系统性提升，证明布线简易性与容错性能间存在权衡关系。
英文摘要
Reaching fault tolerance means scaling qubit counts by orders of magnitude, a jump that conventional superconducting architectures cannot sustain without solving the so-called `wiring problem'. Global control sidesteps this bottleneck, but implementing quantum error correction (QEC) on previously proposed global architectures incurs extremely steep overhead costs, due to the need for separate correction procedures for the computational and auxiliary qubits that comprise the global device. We resolve this by introducing the first globally-controlled architecture with zero qubit overhead. Every physical qubit is a computational qubit, and thus, every qubit is protected under a single error correcting scheme. We identify a class of cyclic stabilizer codes realizable through global iSWAP and single-qubit gates, yielding QEC thresholds nearly seven orders of magnitude larger than previous estimates for globally-controlled arrays. We further show these thresholds improve systematically as the global architecture is augmented with a limited amount of local measurement sites, demonstrating a trade-off between wiring simplicity and fault-tolerant performance.
Comments7+9 pages, 3+2 figures
