存在缺陷的表面码在偏置噪声下的X-Z轮调度
X-Z Round Scheduling for the Surface Code with Defects under Biased Noise
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中文总结 AI 辅助
该研究针对含缺陷的表面码在偏置噪声下，提出优化X-Z校验轮次调度比例的方法，可显著降低逻辑错误率，且该方法的益处也适用于受CNOT串扰的偏置噪声架构。
中文摘要 AI 辅助
容错量子计算（FTQC）依赖量子纠错（QEC）码，这类码通过将逻辑量子比特编码到多个物理量子比特上以检测和纠正错误。表面码是研究最广泛的码之一，原因在于其具备高错误阈值、存在高效解码器，以及硬件友好的特性：它是平面二维布局，具有最近邻连接性。然而在实际应用中，固态量子处理器的制造会引入硬件缺陷，产生缺陷量子比特和耦合器，必须将其弃用。将表面码适配这些缺陷通常需要在不同轮次中而非同时测量X型和Z型校验。本研究探讨了偏置噪声系统下最优的X型与Z型校验轮次调度比例。我们的结果明确了噪声偏置、码距、缺陷率等关键架构参数如何影响逻辑错误率。我们提供了如何直接从设备校准数据确定最优调度比例的见解，使制造商无需大量模拟即可最大化性能。对于中等偏置噪声下的距离-13表面码，我们的方法在缺陷率为1%时可将逻辑错误率降低多达4.25倍，在缺陷率为2%时可降低多达8.46倍。此外，我们证明轮次调度的益处不仅限于缺陷硬件场景：在受CNOT串扰影响的偏置噪声架构中，分离X和Z测量轮次可将逻辑错误率降低多达4.5倍。
英文摘要
Fault-tolerant Quantum Computing (FTQC) relies on Quantum Error Correction (QEC) codes that encode logical qubits across many physical qubits to detect and correct errors. The surface code is among the most widely studied codes due to its high error threshold, the existence of efficient decoders, and hardware-friendly properties: a planar, two-dimensional layout with nearest-neighbor connectivity. In practice, however, the fabrication of solid-state quantum processors introduces hardware defects, resulting in defective qubits and couplers that must be discarded. Adapting the surface code to these defects often requires measuring the $X$- and $Z$-type checks in separate rounds rather than simultaneously. In this work, we investigate the optimal $X$-to-$Z$ checks round-scheduling ratio under biased noise systems. Our results characterize how key architectural parameters, such as noise bias, code distance, and defect rate, impact the logical error rate. We provide insights into how to determine the optimal scheduling ratio directly from device calibration data, enabling manufacturers to maximize performance without extensive simulations. Our approach reduces the logical error rate by up to $4.25\times$ at a $1\%$ defect rate and up to $8.46\times$ at a $2\%$ defect rate for a distance-$13$ surface code under moderately biased noise. Furthermore, we demonstrate that the benefits of round-scheduling extend beyond the defective-hardware setting. In biased-noise architectures subject to CNOT crosstalk, separating $X$ and $Z$ measurement rounds yields up to $4.5\times$ reduction in logical error rate.
