AI 中文总结
本研究提出统一框架结合门与线切割，通过门分组实现联合切割，将切割位置问题转化为可扩展图划分任务，为大规模电路高效识别近最优切割位置并提供诊断反馈以降低采样开销。
AI 中文摘要
量子电路切割通过将电路划分为独立子电路，使有限量子比特数的设备能够执行大规模电路，但这会引入随切割数量指数增长的采样开销，因此切割位置的选择对实际电路切割至关重要，而确定最优切割位置在电路规模增大时仍具有计算挑战性。此外，现有电路切割方法通常独立处理门切割与线切割，而结合两种切割方式的方法未利用联合切割的优势，即识别公共门组并对其联合切割以降低开销。本研究提出一种统一框架，在单一划分策略中结合门切割与线切割，实现更高效的电路分解，还通过新颖的门分组技术纳入联合切割，进一步降低采样开销。通过将切割位置问题表述为可扩展图划分任务，该方法能为大规模电路高效识别近最优切割位置，还提供电路是否适合切割的诊断反馈。
英文摘要
Quantum circuit cutting enables the execution of large circuits on devices with a limited number of qubits by partitioning circuits into independent subcircuits. However, this introduces a sampling overhead, which grows exponentially with the number of cuts, rendering the choice of cut placements critical for practical circuit cutting. Determining optimal cut placements remains computationally challenging, particularly as circuits grow in size. Additionally, existing circuit cutting approaches typically treat gate and wire cuts independently. Those combining both cutting approaches, however, do not take advantage of joint cutting, i.e., identifying common gate groups and cutting them jointly for a reduced overhead. This work presents a unified framework that combines gate and wire cutting within a single partitioning strategy, enabling more efficient circuit decompositions. Moreover, our approach incorporates joint cutting via a novel gate grouping technique, further reducing sampling overhead. By formulating the cut placement problem as a scalable graph partitioning task, our method efficiently identifies near-optimal cut placements for large circuits, also providing diagnostic feedback on whether circuits are suitable for cutting.
