AI 中文总结
针对异构多核SoC分布式HPC模块导致性能数据处理复杂的问题，提出含EVU与APMU的集中式架构，在RISC-V SoC平台实现并通过案例验证其有效性。
AI 中文摘要
硬件性能计数器（HPC）被广泛用于在实时系统中实现事件驱动的软件机制，如引导优化、性能分析和动态资源管理。然而，在现代嵌入式片上系统（SoC）中，不同组件——包括处理器、加速器、互连和内存控制器——通常实现独立且异构的HPC模块。这种分布式监控基础设施需要多个软件接口，使系统范围内性能数据的收集、同步和关联变得复杂。本研究提出一种集中式性能监控架构，以高效收集、关联和处理多个硬件组件的架构事件。该设计引入事件监控单元（EVU），用于捕获微架构事件并将其转发至高级性能监控单元（APMU）；APMU集成可编程计数器和专用处理单元，以支持灵活的事件驱动软件机制。研究人员将该设计实现于基于AXI4的系统，并集成至缺乏高级跨组件性能监控支持的基于RISC-V的SoC平台，通过实时资源调控、应用分析和计数器归因的案例研究验证了该方法的有效性。
英文摘要
Hardware Performance Counters (HPCs) are widely used to enable event-driven software mechanisms such as profile guided optimization, performance analysis, and dynamic resource management in real-time systems. However, in modern embedded System-on-a-Chip (SoCs), different components - including processors, accelerators, interconnects, and memory controllers - typically implement separate and heterogeneous HPC modules. This distributed monitoring infrastructure requires multiple software interfaces and complicates the collection, synchronization, and correlation of performance data across the system. In this work, we propose a centralized performance monitoring architecture to efficiently collect, correlate, and process architectural events across multiple hardware components. Our design introduces Event Monitoring Units (EVUs) that capture and forward microarchitectural events to an Advanced Performance Monitoring Unit (APMU). The APMU integrates programmable counters and a specialized processing element to support flexible, event-driven software mechanisms. We implement our design for an AXI4-based system and integrate it into a RISC-V based SoC platform, which lacks advanced cross-component performance monitoring support. We demonstrate the effectiveness of our approach through case studies on real-time resource regulation, application profiling, and counter attribution.
Comments14 Pages, 9 Figures, submitted to EMSOFT2026
