AI 中文总结
本文提出一种新型符号执行框架，利用可捕捉牵引效应等的分析型门延迟模型，计算数字电路路径的符号延迟表达式，引入符号剪枝方法以减少组合爆炸，实现时序属性的路径敏感推理与路径优化。
AI 中文摘要
基于仿真的数字集成电路动态时序分析（DDTA）为传统模拟SPICE仿真提供了更快的替代方案。然而，要获得在准确性上具备合理竞争力的时序预测，DDTA需要超出当前最先进工具所用标准纯延迟或惯性延迟模型的门延迟模型。分析型门延迟模型的最新进展现已能捕捉如牵引效应和多输入切换等影响，为时序分析开辟了新的可能性，超越了基于仿真的方法，实现了详尽的探索。本文提出了一种新型符号执行框架的核心要素，该框架利用此类分析型延迟模型，针对输入转换的特定排序自动计算数字电路中所有路径的符号延迟表达式。为减少组合爆炸，我们引入了符号剪枝方法，该方法还支持对时序属性的路径敏感、目标驱动推理，以及特定电路路径的分析型优化。
英文摘要
Simulation-based dynamic timing analysis of digital integrated circuits (DDTA) offers a faster alternative to traditional analog SPICE simulations. To achieve timing predictions that are reasonably competitive in terms of accuracy, however, DDTA mandates gate delay models that go beyond the standard pure or inertial delay models used in state-of-the-art tools. Recent advances in analytic gate delay models, which now also capture effects like drafting and multi-input switching, unlock new possibilities for timing analysis, which go way beyond simulation-based approaches towards an exhaustive exploration. In this paper, we present the cornerstones of a novel symbolic execution framework, which utilizes such analytic delay models for automatically computing symbolic delay expressions for all paths in a digital circuit, for some given ordering of the input transitions. To reduce combinatorial explosion, we introduce symbolic pruning methods that also enable path-sensitive, goal-driven reasoning about timing properties and analytic optimization of specific circuit paths.
