AI 中文总结
针对现有量子纠错主解码器无法利用预解码稀疏性的问题，提出Zero-G解码器，其可动态权衡延迟与精度，实现10倍延迟提升，支持CPU和FPGA异构部署，适配大码距与多逻辑量子比特场景。
AI 中文摘要
容错量子计算需要经典解码器能与底层硬件同步，将量子纠错的症候测量结果快速转换为纠错操作，避免指数级延迟堆积。为满足实时性要求，预解码器作为分层解码方案的一部分出现，用于解决简单的局部错误，再将更稀疏的残留症候传递给主解码器。理论上预解码应能加快主解码速度，但实际中加速效果有限，因为现有主解码器设计用于解码密集症候，无法利用预解码带来的稀疏性。为解决该问题，本文提出Zero-G，一款专为与预解码器协同工作设计的主解码器。作为随机近似最小权完美匹配（MWPM）解码器，Zero-G可利用稀疏残留症候，动态权衡延迟与精度，而非依赖非此即彼的运行时-精度权衡。通过将硬件控制与解码核心解耦，Zero-G可在FPGA和CPU上异构部署，无需维护独立实现。Zero-G在匹配精度下，相较现有主解码器实现了10倍延迟提升，在码距d=15时最坏情况解码延迟低于350ns，且可在单个128核CPU上扩展至640个逻辑量子比特，在单个AMD Versal V80 FPGA上扩展至32个逻辑量子比特。
英文摘要
Fault-tolerant quantum computing requires classical decoders that keep pace with the underlying hardware, translating syndrome measurements into corrections fast enough to avoid an exponential backlog. To meet this real-time constraint, pre-decoders have emerged as part of a hierarchical decoding approach to resolve simple, local errors before passing a sparser residual syndrome to a strong decoder. While pre-decoding should, in theory, speed up the strong decoder, in practice, the speedup is only marginal, since existing strong decoders are designed to decode dense syndromes and cannot exploit the sparsity provided by pre-decoders. To address this, we present Zero-G, a strong decoder designed for use alongside pre-decoders. As a stochastic approximate minimum-weight perfect matching (MWPM) decoder, Zero-G exploits sparse residual syndromes, dynamically trading latency for accuracy rather than relying on an all-or-nothing runtime-accuracy trade-off. By decoupling hardware control from the decoding core itself, we enable heterogeneous deployment across both FPGAs and CPUs without maintaining separate implementations. Zero-G achieves a $10\times$ latency improvement over existing strong decoders at matching accuracy, with worst-case sub-350ns decoding at code distances up to d=15, while scaling to 640 logical qubits on a single 128-core CPU and 32 logical qubits on a single AMD Versal V80 FPGA.
