AI 中文总结
本文针对8级RISC-V软处理器，对比分析RV32与RV64架构下FreeRTOS的延迟差异，发现RV64任务切换和抢占的周期开销更高，并开源了相关代码。
AI 中文摘要
尽管许多商用RISC-V平台提供实时操作系统支持，但解释如何在定制的裸机RISC-V软处理器上启用抢占式RTOS的实际示例仍然有限，这使得从简单硬件实现示例中难以理解处理器微架构、中断处理与RTOS上下文切换之间的交互。本文在定制的8级RV32/RV64 RISC-V软处理器上呈现FreeRTOS的设计与评估，该处理器具备机器模式CSRs、CLINT定时器、陷阱与异常控制逻辑以及所需的上下文切换路径。利用该平台，我们在相同的微架构组织和固件结构下，使用两个源自Rhealstone的延迟微基准测试——任务切换和任务抢占（通过mcycle计数器测量），对比RV32与RV64。RV64在任务切换和抢占中分别需要多36.6%和17.7%的周期。指令级分析将此开销归因于翻倍的RV64陷阱帧、更宽的基于指针的内核数据结构以及64位调度器优先级处理。RTL、固件和基准代码以开源形式发布。
英文摘要
Although many commercial RISC-V platforms provide real-time operating system support, practical examples that explain how to enable a preemptive RTOS on a custom bare-metal RISC-V soft processor remain limited, leaving the interaction between processor microarchitecture, interrupt handling, and RTOS context switching difficult to understand from simple hardware implementation examples. This paper presents the design and evaluation of FreeRTOS on custom 8-stage RV32/RV64 RISC-V soft processors with machine-mode CSRs, a CLINT timer, trap and exception control logic, and the required context-switch path. Using this platform, we compare RV32 and RV64 under the same microarchitectural organization and firmware structure using two Rhealstone-derived latency microbenchmarks, task switching and task preemption, measured with the mcycle counter. RV64 requires 36.6% and 17.7% more cycles for task switching and preemption, respectively. Instruction-level analysis attributes this overhead to the doubled RV64 trap frame, wider pointer-based kernel data structures, and 64-bit scheduler priority handling. The RTL, firmware, and benchmark code are released as open source.
Comments5 pages, 1 figure. Accepted for presentation at APCCAS 2026; to be presented on October 26, 2026
