PROPEL：面向大规模光子集成芯片的内存驱动、自适应矢量流场路由器及工艺感知波导生成技术
PROPEL: A Memory-Driven, Adaptive Vector-Flow-Field Router with Process-Aware Waveguide Generation for Large-Scale Photonic Integrated Circuits
AI总结：
PROPEL是面向大规模PIC的内存驱动自适应矢量流场路由框架，可处理多类约束，在多数无源路由案例中速度领先，还支持多种高级功能以应对异构布局需求。
AI中文摘要：
光子集成芯片（PIC）的规模和路由复杂度正不断提升，其驱动因素包括光子计算、光交换、可编程干涉仪网格、波长路由光片上网络以及芯片间光互连。当设计接近数千个光子组件时，手动波导规划变得不切实际，因为路由必须满足几何、光学、电学和制造约束。本文提出了光子路由优化与布局引擎（PROPEL），这是一种用于大规模PIC设计的内存驱动、原生加速自适应矢量流场路由框架，具备工艺感知波导生成能力。PROPEL基于有界矢量流场算法和设计规则检查（DRC）验证构建路由内核，该内核支持无源光路由、有源光-电路由以及拓扑驱动的网络分配。C++用于加速场和路由计算，Python则执行详细的DRC重放、合法性检查、路由提交以及基于GDSFactory的几何生成。与最先进的路由解决方案相比，在18个共享无源路由案例中，PROPEL在17个案例上速度更快，中位数加速比为2.6倍，几何平均加速比为2.5倍，同时保持零设计规则违规。PROPEL还支持长度、延迟和光程匹配、工艺映射感知波导生成、路由内存复用、选择性拆-重路由以及GDS级合法性重放，这些能力可应对异构PIC布局，其中需同时处理光学、电学、工艺、拓扑、匹配和可制造性约束。
英文摘要：
Photonic integrated circuits (PICs) are increasing in scale and routing complexity, driven by photonic computing, optical switching, programmable interferometer meshes, wavelength-routed optical networks-on-chip, and chip-to-chip optical interconnects. Manual waveguide planning becomes impractical as designs approach thousands of photonic components because routing must satisfy geometric, optical, electrical, and manufacturing constraints. This paper presents the Photonic Routing Optimization and Placement Engine (PROPEL), a memory-driven, native-accelerated adaptive vector-flow-field routing framework with process-aware waveguide generation for large-scale PIC design. PROPEL builds a routing kernel based on a bounded vector-flow-field algorithm and DRC validation. The same kernel supports passive optical routing, active optical-electrical routing, and topology-driven net assignment. C++ accelerates field and routing calculations, while Python performs detailed DRC replay, legality checking, route commitment, and GDSFactory-based geometry generation. Compared with state-of-the-art routing solutions, PROPEL is faster on 17 of 18 shared passive-routing cases, with a median speedup of 2.6x and a geometric-mean speedup of 2.5x, while maintaining zero design-rule violations. PROPEL also supports length, delay, and optical-path-length matching, process-map-aware waveguide generation, route-memory reuse, selective rip-up/reroute, and GDS-level legality replay. These capabilities address heterogeneous PIC layouts where optical, electrical, process, topology, matching, and manufacturability constraints must be handled together.
