面向柔性IGZO模拟混合信号系统的低功耗基于PLL的时钟稳定技术
Low-Power PLL-Based Clock Stabilization for Flexible IGZO AMS Systems
查看机构详情
- Karlsruhe Institute of Technology（卡尔斯鲁厄理工学院）
- National Technical University of Athens（雅典国立技术大学）
机构由 AI 辅助整理，请以论文原文为准。
浏览论文内容
中文总结 AI 辅助
本文针对柔性IGZO AMS系统的时钟稳定需求，设计了首款适配a-IGZO TFT技术的低功耗PLL，其功耗与面积优势显著，在多类IGZO系统上实现了良好的时钟稳定性。
中文摘要 AI 辅助
柔性电子（FE）平台依赖模拟和混合信号（AMS）电路，包括生物传感器、读出前端和模数转换器，这些电路主导着功能和能耗，使得片上时钟生成成为一项必要但功耗关键的功能。现有的基于振荡器的解决方案存在不受限的工艺、电压和温度（PVT）漂移问题，会降低信号完整性，而替代时钟源的功耗可达系统总功耗预算的90%，使其无法应用于FE平台，进而将时钟生成提升为主要的功耗和能效设计约束。本文提出了首个专为仅含n型非晶铟镓锌氧化物（a-IGZO）薄膜晶体管（TFT）技术设计的锁相环（PLL）架构，解决FE特有的约束，如缺少p型器件、载流子迁移率有限以及强PVT变异性。该设计不以高精度频率合成为目标，而是作为低带宽时间稳定器运行：基于自由运行环形振荡器的压控振荡器（VCO）由极简电荷泵反馈环路进行软调节，以限制长期频率漂移，无需连续的高质量外部参考。所提出的PLL支持1 kHz至300 kHz的频率，占用面积为0.0115-0.0233 mm²，功耗为0.115-0.153 mW。与现有基于振荡器的FE时钟解决方案相比，该架构功耗降低400倍以上，与柔性VCO相比面积缩小1500倍以上，与环形振荡器解决方案相比面积缩小390倍以上。在四个代表性的已发表IGZO AMS系统上进行了验证，所提出的PLL实现了2.24 ns的均方根周期抖动，以及1000 ppm以内的长期频率精度，为FE平台提供了基于参考的时钟稳定性。
英文摘要
Flexible electronics (FE) platforms rely on analog and mixed-signal (AMS) circuits - biosensors, readout front-ends, and analog-to-digital converters - that dominate both functionality and energy consumption, making on-chip clock generation an essential yet power-critical function. Existing oscillator-based solutions suffer from unbounded process, voltage, and temperature (PVT) drift that degrades signal integrity, while alternative clock sources can consume up to 90% of the total system power budget, rendering them inapplicable to FE platforms and elevating clock generation to a primary power and energy-efficiency design constraint. This paper presents the first phase-locked loop (PLL) architecture designed for n-type-only amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) technology, addressing FE-specific constraints such as the absence of p-type devices, limited carrier mobility, and strong PVT variability. Rather than targeting high-precision frequency synthesis, the proposed design operates as a low-bandwidth temporal stabilizer: a free-running ring-oscillator-based voltage-controlled oscillator (VCO) is softly regulated by a minimal charge-pump feedback loop to bound long-term frequency drift without requiring a continuous high-quality external reference. The proposed PLL supports frequencies from 1 kHz to 300 kHz while occupying 0.0115-0.0233 mm2 and consuming 0.115-0.153 mW. Compared with prior oscillator-based FE clocking solutions, our architecture reduces power by more than 400x while achieving footprint reductions exceeding 1500x compared to flexible VCOs, and more than 390x with respect to ring-oscillator solutions. Validated across four representative published IGZO AMS systems, the proposed PLL achieves an rms period jitter of 2.24 ns and a long-term frequency accuracy within 1000 ppm, providing reference-anchored clock stability in FE platforms.
