AI 中文总结
本研究提出利用时间并行性实现结合Union-Find算法的三明治译码方法的微架构及ASIC实现，可降低量子纠错译码延迟并保持逻辑错误阈值。
AI 中文摘要
在容错量子计算的研究中，低延迟量子纠错（QEC）对于防止症候测量周期内的快速误差积累至关重要。本研究提出一种微架构，利用时间并行性实现结合Union-Find算法的三明治译码方法，并给出其ASIC实现。通过逻辑综合与仿真表明，在码距d=21时，与传统批量Union-Find译码器相比，所提译码器平均延迟降低35%，同时在现象学噪声下保持约1.5%的相当逻辑错误阈值。
英文摘要
In the pursuit of fault-tolerant quantum computing, low-latency quantum error correction (QEC) is essential to prevent rapid error accumulation within the syndrome measurement cycle. In this work, we propose a microarchitecture that implements the sandwich decoding method using the Union-Find algorithm by exploiting temporal parallelism, and we present an ASIC implementation. Through logic synthesis and simulation, we show that the proposed decoder achieves an average latency reduction of 35% at code distance d = 21 compared with a conventional batch Union-Find decoder, while maintaining a comparable logical error threshold of approximately 1.5% under phenomenological noise.
Comments11 pages, 11 figures, 2 tables. Accepted at IEEE International Conference on Quantum Computing and Engineering (QCE) 2026
