AI 中文总结
本文针对模块化量子架构，研究带噪声接口的容错逻辑操作，开发高效分布式容错逻辑GHZ态制备协议，为规模化容错量子计算提供定量依据。
AI 中文摘要
模块化量子计算是超越单片设备资源限制实现量子计算规模化的领先范式，该架构中多个量子处理单元（QPU）采用相同或不同的量子比特模态，通过共享纠缠实现互连。本文研究当量子比特采用旋转表面码编码时，模块接口及单个QPU内的误差对容错计算的影响；除逻辑存储基准外，我们对通过连接带噪声贝尔对的QPU间晶格手术实现的容错非局域CNOT门进行电路级模拟，分析其逻辑错误率。结果表明，接口可容忍比QPU内部噪声高一个数量级的噪声，仅轻微降低容错阈值；我们进一步开发了一种制备分布式容错逻辑GHZ态的高效协议，减少了辅助量子比特开销、时间及非局域贝尔对消耗，证明该场景下辅助量子比特最小化等价于相关图上的顶点覆盖问题，并引入了一种寻找低开销解的多项式时间启发式算法。研究结果为分布式量子纠错可在模块化架构中实现规模化容错量子计算提供了定量证据。
英文摘要
Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices. In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates. Our results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold. We further develop an efficient protocol for preparing distributed fault-tolerant logical GHZ states, reducing ancilla overhead, time, and nonlocal Bell-pair consumption. We show that ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and introduce a polynomial-time heuristic algorithm for finding low-overhead solutions. Our results provide quantitative evidence that distributed quantum error correction can enable scalable, fault-tolerant quantum computation in modular architectures.
Comments10 pages, 6 figures
