发表机构
Tencent; School of Integrated Circuits, Peking University; Southwest Jiaotong University; Institute of Electronic Design Automation, Peking University; Beijing Advanced Innovation Center for Integrated Circuits（腾讯; 北京大学集成电路学院; 西南交通大学; 北京大学电子设计自动化研究所; 北京集成电路高精尖创新中心）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
GoGoTB是实现端到端验证闭合的智能体式RTL验证框架，在8个RTL设计上无需人工干预，实现100%环境生成成功率及多维度高覆盖率，优于现有方法。
AI 中文摘要
功能验证占据了集成电路（IC）前端工程的主要工作量，一个未被发现的漏洞若漏到流片环节，可能导致高昂的重新设计成本。近期的大语言模型（LLM）为这一流程的自动化提供了新机遇，但现有的基于LLM的方法通过独立的单轮调用生成每个组件，缺乏共享上下文，导致接口不匹配问题无法被检测，且报告的覆盖率与规范要求脱节。为解决这些挑战，本文提出GoGoTB，一个智能体式框架，通过三个子系统实现端到端的验证闭合：智能体执行控制层、可演化知识系统以及规范驱动的覆盖闭合。执行控制层在每个工具和阶段边界将确定性执行与LLM推理分离；知识系统按需提供方法论和设计特定的专业知识；覆盖框架将每个覆盖点绑定到已命名的规范行为，使每个剩余缺口都有可诊断的根本原因和针对性的补救措施。在8个寄存器传输级（RTL）设计上进行测试，无需任何人工干预，GoGoTB实现了100%的环境生成成功率，平均达到98.4%的行覆盖率、97.2%的分支覆盖率、97.0%的翻转覆盖率以及83.2%的功能覆盖率。此前没有任何工作能在相同基准上成功生成完整的验证环境或达到有意义的覆盖率。
英文摘要
Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin. Recent large language models (LLMs) offer new opportunities to automate this process, yet existing LLM-based approaches generate each component through independent single-turn calls with no shared context, leaving interface mismatches undetected and reported coverage disconnected from specification requirements. To address these challenges, we present GoGoTB, an agentic framework that achieves end-to-end verification closure through three subsystems: an agentic execution control layer, an evolvable knowledge system, and specification-grounded coverage closure. The execution control layer separates deterministic enforcement from LLM reasoning at every tool and stage boundary. The knowledge system dispatches methodology and design-specific expertise on demand. The coverage framework anchors every bin to a named specification behavior so that each residual gap has a diagnosable root cause and a targeted remedy. Tested on 8 register transfer level (RTL) designs without any human intervention, GoGoTB achieves 100\% environment generation success and averages 98.4\% line, 97.2\% branch, 97.0\% toggle, and 83.2\% functional coverage. No prior work successfully generates a complete verification environment or achieves meaningful coverage on the same benchmarks.
Comments9 pages, 7 figures, 3 tables. Xin Xin and Jincheng Lou contributed equally to this work and share first authorship
