AI 中文总结
研究如何减轻65纳米单多晶硅浮栅模拟内存计算中保留损失对推理精度的影响，采用电路级补偿技术和算法级批量归一化重新校准，经实验验证编程60天后能让推理精度恢复到基线的2 - 4%以内。
AI 中文摘要
我们通过实验和系统级模拟表明，利用电路级补偿技术和算法级的批量归一化重新校准，能够成功减轻保留损失对推理精度下降的影响。实验在标准65纳米CMOS制造的用于模拟内存计算的单多晶硅浮栅模拟非易失性存储器阵列上进行。我们使用经实验校准的保留损失统计模型评估对VGG - 10/CIFAR - 10和WideResNet - 28 - 10/CIFAR - 100等神经网络模型的系统级影响。结果表明，编程60天后，组合缓解技术能使推理精度恢复到基线的2 - 4%以内。
英文摘要
We show with experiments and system-level simulations that it is possible to successfully mitigate the impact of retention loss on inference accuracy degradation by using both circuit-level compensation techniques and batch normalization recalibration at the algorithmic level. Experiments are performed on a single-poly floating-gate (FG) analog non-volatile memory array for analog in-memory computing fabricated in a standard 65 nm CMOS. We use a model of retention-loss statistics calibrated with experiments to evaluate the system-level impact on neural network models such as VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100. We show that, after 60 days since programming, combined mitigation techniques enable to recover the baseline inference accuracy within 2-4%
Comments4 pages, 3 figures
