用于半导体晶圆制造的动态多标准瓶颈严重度指数(DMBSI)：一种针对重入式生产系统的遗传优化框架
Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI) for Semiconductor Wafer Manufacturing: A Genetically Optimised Framework for Reentrant Production Systems
- Ulster University（阿尔斯特大学）
- Seagate Technology（希捷科技）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
研究针对半导体晶圆制造的独特特性，提出数据驱动的动态多标准瓶颈严重度指数(DMBSI)，经遗传算法优化，能分析多诊断信号及返工影响，实验验证其优于其他方法，还能识别瓶颈迁移模式并进行假设分析。
AI中文摘要：
晶圆制造具有独特特性，包括重入式工艺流程、可变瓶颈和高度可变的工艺条件。为识别半导体晶圆制造中每个时刻最严重的瓶颈，本研究提出动态多标准瓶颈严重度指数(DMBSI)，这是一种新的数据驱动方法，用于分析周期时间对工艺参数变化的多个诊断信号以及返工对周期时间的影响，以生成可解释的统一瓶颈严重度度量。使用从希捷科技运营的商业200mm晶圆制造线的22个晶圆生产批次收集的制造执行系统(MES)日志对DMBSI进行实验验证。采用5折交叉验证，遗传算法优化的DMBSI与观察到的周期时间贡献的皮尔逊相关系数r = 0.80，比专家启发式基线(r = 0.74)提高了8.1%，显著优于约束理论(TOC; r = 0.60)和价值流映射(VSM; r = -0.30)。此外，DMBSI独特的时间窗口组件能够识别时间瓶颈迁移模式，从早期生产窗口中与介电沉积步骤相关的主要约束转移到后期生产窗口中与过度和不足检查相关的约束。综合假设分析表明，排名最高的瓶颈步骤等待时间减少50%将使平均周期时间减少7.2%，前五个瓶颈步骤的综合潜在减少约为19%。
英文摘要：
Wafer fabrication exhibits unique characteristics, including reentrant process flows, variable bottlenecks, and highly variable process conditions. In order to identify the most severe bottleneck at each moment in time for semiconductor wafer fabrication, this research presents the Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI), a new, data-driven methodology for analysing multiple diagnostic signals of cycle time to changes in process parameters, and the impact of reworks on cycle time in order to generate an interpretable, unified measure of bottleneck severity. The experimental validation of DMBSI was conducted using Manufacturing Execution System (MES) logs collected from 22 wafer production lots at a commercial 200 mm wafer fabrication line operated by Seagate Technology. Using 5-fold cross-validation, the GA-optimised DMBSI achieves a Pearson correlation of r = 0.80 with observed cycle-time contributions, representing an 8.1% improvement over the expert heuristic baseline (r = 0.74) and substantially outperforming the Theory of Constraints (TOC; r = 0.60) and Value Stream Mapping (VSM; r = -0.30). Furthermore, the unique time-windowed component of DMBSI enabled the identification of temporal bottleneck migration patterns, which shifted from the dominant constraints associated with dielectric deposition steps in the early production windows to those associated with over- and under-inspection in the later production windows. The integrated what-if counterfactual analysis demonstrated that a 50% reduction in waiting time at the top-ranked bottleneck step would reduce the mean cycle time by 7.2%, with the top five bottleneck steps offering a combined potential reduction of approximately 19%.
