用于复杂囚禁离子架构的高效大语言模型生成的穿梭编译器
Efficient LLM-Generated Shuttling Compilers for Complex Trapped-Ion Architectures
- Johannes Gutenberg University（美因茨大学）
- Saarland University（萨尔大学）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
研究利用大语言模型Claude Opus 4.7和Claude Fable 5为复杂囚禁离子架构生成穿梭编译器，经实验对比，该编译器能有效减少穿梭时间步，无需人工算法工程，大幅缩短新架构开发时间。
AI中文摘要：
囚禁离子量子计算机依赖穿梭编译器，将输入算法转换为给定架构内离子量子比特运动序列。本文首次研究使用单个前沿大语言模型Claude Opus 4.7从书面规范生成并迭代优化穿梭编译器的完整Python代码。先为线性分段阱编写编译器，扩展到有结的阱，最终实现对一大类连通阱图的高效编译。用通用量子电路套件将大语言模型生成的编译器与手工制作的最先进编译器进行基准测试。结果表明，未修改的前沿大语言模型可生成实用、正确且有竞争力的穿梭编译器，无需额外人工算法工程，将新架构开发时间从数月缩短至数天。
英文摘要：
Trapped-ion quantum computers rely on shuttling compilers, which cast an input algorithm into a sequence of ion-qubit movements within a given architecture. We present the first study in which a single frontier large language model (LLM), Claude Opus 4.7, generates and iteratively refines the full Python code of shuttling compilers from written specifications. We start with a compiler for (i) a linear segmented trap, extend it to (ii) a trap with junctions, and finally achieve efficient compilation for (iii) a broad class of connected trap graphs. The compilers for the more general cases are seeded with code from the previous ones. We benchmark the LLM-generated compilers against state-of-the-art hand-crafted ones using a common suite of quantum circuits. The number of shuttling timesteps is reduced by up to 76% for (i) and up to 39% for (ii). For the broad case (iii) of freely connected architectures, we find large variations in the required number of shuttling timesteps, depending on the connectivity. A densely connected, junction-rich architecture yields an order-of-magnitude reduction in shuttling timesteps compared to a corridor-like one. Repeating the complete generation and evaluation with a second frontier LLM, Claude Fable 5, reproduces these findings, with the Fable 5 compilers surpassing the hand-crafted ones more often on the largest circuits. Our results show that an unmodified frontier LLM can produce working, correct, and competitive shuttling compilers without additional manual algorithmic engineering, thus reducing the development time for new architectures from several months to a few days.
