AI 中文总结
研究在定点傅里叶特征自动调制分类器中学习特征门控的效果，通过特定架构和训练方法，在FPGA上评估其对分类准确率及硬件资源的影响，发现学习门控增加成本且未提升准确率。
AI 中文摘要
学习特征重加权可在软件中改进自动调制分类（AMC），但在FPGA上实现时会带来额外运算和延迟。本文在紧凑型定点分类器中衡量此权衡，该分类器使用24个稀疏DFT能量特征、8个相位/统计特征和一个32 - 128 - 11多层感知器。第二种架构在分类器前插入一个学习的32元素、8位、输入依赖门。使用训练后量化（PTQ）和量化感知训练（QAT）及两个匹配训练种子训练门控和非门控模型。将八个结果检查点独立编译到英特尔Cyclone V FPGA上，并在352,000次物理板分类上评估。非门控模型在所有四次匹配门比较中测试准确率更高，PTQ下门控减非门控平均差异为 - 0.784个百分点，QAT下为 - 0.616个百分点。QAT的效果在两个训练种子间方向改变。在硬件中，门平均增加1,318个自适应逻辑模块（ALM）、1,557个寄存器、4个DSP块和3,140个处理周期。所有352,000次板预测与独立整数参考完全一致，来自一个训练种子的3,760个捕获中间值也匹配。对于此特征表示和实现，学习门控增加FPGA成本却未提高分类准确率。
英文摘要
Learned feature reweighting can improve automatic modulation classification (AMC) in software, but the same operation introduces additional arithmetic and latency when implemented on an FPGA. This work measures that trade-off in a compact fixed-point classifier using 24 sparse DFT-energy features, 8 phase/statistical features, and a 32-to-128-to-11 multilayer perceptron. A second architecture inserts a learned 32-element, 8-bit, input-dependent gate before the classifier. Gated and ungated models are trained using post-training quantization (PTQ) and quantization-aware training (QAT) with two matched training seeds. The resulting eight checkpoints are compiled independently for an Intel Cyclone V FPGA and evaluated over 352,000 physical-board classifications. Ungated models achieve higher test accuracy in all four matched gate comparisons, with mean gated-minus-ungated differences of -0.784 percentage points under PTQ and -0.616 percentage points under QAT. The effect of QAT changes direction between the two training seeds. In hardware, the gate adds an average of 1,318 adaptive logic modules (ALMs), 1,557 registers, 4 DSP blocks, and 3,140 processing cycles. All 352,000 board predictions agree exactly with an independent integer reference, and 3,760 captured intermediate values from one training seed also match. For this feature representation and implementation, learned gating increases FPGA cost without improving classification accuracy.
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