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架起 AQFP 技术合法化与物理设计的桥梁:通过宽度-深度乘积最小化实现布局感知缓冲器和分离器插入

Bridging AQFP Technology Legalization and Physical Design: Layout-Aware Buffer and Splitter Insertion via Width--Depth Product Minimization

Robert S. Aviles, Ziyu Liu, Madhav Danturthi, Peter A. Beerel

arXiv 2607.23761首次发表:更新:

AI 中文总结

研究 AQFP 技术中缓冲器和分离器插入优化问题,核心方法是将其重新定义为最小化电路宽度-深度乘积,并开发可扩展启发式算法,主要贡献是相比现有方法有效降低了实际设计成本。

AI 中文摘要

绝热量子通量参量管(AQFP)是一种新兴的超导技术,能实现接近香农极限的超低能耗。但其门级流水线和显式扇出约束需通过插入缓冲器和分离器进行技术合法化,以确保路径平衡和信号分配,这成为设计流程中关键且成本高昂的步骤。先前工作聚焦于最小化插入单元数量和逻辑深度,但这些目标无法准确反映最终物理设计成本,而物理设计成本根本上由电路宽度和深度的乘积决定。本文将 AQFP 缓冲器和分离器插入优化重新定义为最小化电路宽度-深度乘积,这是一种布局感知度量,比先前的单元最小化方法更能准确反映物理设计面积。我们首次在此目标下制定缓冲器和分离器插入问题,并证明该问题是 NP 完全问题。为解决此复杂性问题,我们开发了将合法化与该目标相结合的可扩展启发式算法。在标准基准测试上的实验结果表明,与现有方法相比,我们的方法在布局后面积平均减少 30%,结数仅增加 3%,在单个电路上面积减少高达 61%,证明了所提目标在降低实际设计成本方面的有效性。

英文摘要

Adiabatic Quantum Flux Parametron (AQFP) is an emerging superconducting technology that enables ultra-low energy dissipation approaching the Shannon limit. However, its gate-level pipelining and explicit fanout constraints require technology legalization through buffer and splitter insertion to ensure path balancing and signal distribution, becoming a critical and costly step in the design flow. Prior work has focused on minimizing inserted cell count and logic depth, yet these objectives do not accurately capture the final physical design cost, which is fundamentally governed by the product of circuit width and depth. In this article, we redefine AQFP buffer and splitter insertion optimization as minimizing the circuit width--depth product, a layout-aware metric that more accurately captures physical design area than prior cell minimization efforts. We are the first to formulate buffer and splitter insertion under this objective and prove that the resulting problem is NP-complete. To address this complexity, we develop scalable heuristics that integrates legalization with this objective. Experimental results on standard benchmarks demonstrate that our approach achieves an average 30% reduction in post-placement area compared to state-of-the-art methods, with only a 3% increase in junction count, and on individual circuits up to 61% area reduction, demonstrating the effectiveness of the proposed objective in reducing true design cost.

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