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优化Transformer神经网络以在FPGA上进行实时异常检测

Optimizing Transformer Neural Network for Real-Time Outlier Detection on FPGAs

Ilia Sobakinskikh, Paul Alexander Bilokon

arXiv 2607.22786首次发表:更新:

AI 中文总结

研究如何优化Transformer神经网络推理时间用于金融时间序列实时异常检测,探索不同架构在FPGA板上的高效实现,以最小化延迟进行时间序列异常检测。

AI 中文摘要

在这项工作中,我们探索如何有效优化Transformer神经网络的推理时间,并将其应用于金融时间序列的实时异常检测。金融时间序列如资产价格序列,常存在错误或异常值,影响下游数据处理任务。随着数据量显著增加,需要更好的数据清理方法。Transformer在多项任务中表现出色,时间序列建模和异常检测可受益于其架构特点。近年来,如现场可编程门阵列(FPGA)等强大硬件因可重构性和高性能被广泛使用。我们探索用于时间序列建模的不同Transformer架构及其在FPGA板(PYNQ-Z2)上的高效实现,尤其研究其在时间序列异常检测中的应用,并展示如何在FPGA板上高效实现以最小化延迟,代码可通过链接获取。

英文摘要

In this work, we explore how the inference time of a Transformer Neural Network can be efficiently optimized with applications to real-time anomaly detection in financial time series. The financial time series are price series such as asset prices. Unfortunately, the data is often with errors or outliers that make the downstream data processing tasks useless, unstable or even harmful. Moreover, the amount of financial time-series data has been significantly increasing. Hence, there is a need for better data-cleaning methods in terms of accuracy and in terms of processing speed. Transformers as a neural network architecture have achieved superior performances in many tasks such as Natural Language Processing and Computer Vision. Time series modelling and especially anomaly detection tasks can benefit from the features of transformers architecture in multiple ways, including the capacity to capture long-range dependencies and interactions. Increasingly powerful hardware, such as field-programmable gate arrays (FPGAs), have seen increasing usage in recent years due to their reconfigurability and high performance. They can be efficiently utilized to speed up the computations of the Transformer architecture. We explore different Transformer architectures for time series modelling and how they can be efficiently implemented on an FPGA board (PYNQ-Z2). In particular, we examine the application of Transformers to detect anomalies in time series and we show how they can be efficiently implemented on an FPGA board to minimize latency. The code is available at https://github.com/thxi/icl_thesis

Journal refThe Journal of FinTech, Vol. 5, No. 1, 2550001 (2025)

DOI:10.1142/S2705109925500014

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