AI 中文总结
研究如何优化容错态制备电路，利用电路规范算子形式将标志电路构建表示为整数线性规划，能构建门数等于或低于现有技术的电路，还能检测多达三个错误，并推导了Steane纠错器件，测试得到较低错误率。
AI 中文摘要
后选稳定器态制备是容错量子计算中的必要子程序，减少容错制备稳定器态所需的门数可减少求解时间并提高可靠性。对于大码，现有两种自动容错态制备方法。本文利用电路规范算子形式将标志电路构建表示为整数线性规划来优化态制备电路，能构建门数等于或低于现有技术的电路，还能检测多达三个错误。我们用此技术为[[24, 10, 4]]两体群代数码推导了Steane纠错器件，并在量子计算机上测试，得到逻辑块错误率约为0.00014（每个逻辑量子比特约0.000014），约1.6%的测量因权重二错误而被后选。
英文摘要
Post-selected stabilizer state preparation is a necessary subroutine in fault-tolerant quantum computation, both for initialization of logical qubits, and for logical-ancilla-based error correction gadgets (e.g. Steane and Knill). Therefore, reducing the number of gates needed to prepare a stabilizer state fault-tolerantly can simultaneously reduce time-to-solution and increase reliability. For small, low-distance codes such as the [[7, 1, 3]] Steane code, circuits with low gate counts can be found by inspection. This becomes impractical for larger codes, necessitating automation. There are two state-of-the-art methods for automated fault-tolerant state preparation, SAT-based stabilizer measurement and flag-at-origin. In this work, we optimize state preparation circuits using the circuit gauge operator formalism to express the construction of flag circuits as an integer linear program. This allows the construction of circuits with equal or lower gate count than the state of the art, while detecting up to three errors. We use this technique to derive a Steane error correction gadget for the [[24, 10, 4]] two-block group algebra code, and test it on Quantinuum's System Model H2 quantum computer with 10,000 shots, resulting in a logical block error rate ~0.00014 (~0.000014 per logical qubit), with ~1.6% of the shots post-selected due to weight-two errors.
