AI 中文总结
研究卡利纳分组密码，探索多种设计架构实现其加密等功能，权衡面积与延迟，提出硬件缩减技术及低能耗替代设计，给出针对边信道分析和故障注入攻击的对策，在65纳米专用集成电路芯片验证，实现隐藏泄漏和减轻攻击等。
AI 中文摘要
卡利纳分组密码是乌克兰加密标准，于2007年至2010年通过全国竞赛选出并于2015年获批。虽有软件实现，但算法的硬件高效实现（即加速器）不存在。本文探索多种设计架构来实现其加密、解密及统一加密/解密功能，权衡面积与延迟。提出硬件缩减技术并引入低面积、延迟和能耗的替代设计，目标是专用集成电路。还给出针对边信道分析和故障注入攻击的硬件高效设计及对策。在65纳米专用集成电路芯片中验证这些实现。实验结果证实探索不同需求设计搜索空间的替代设计的必要性。所提架构能通过随机化操作执行隐藏功率边信道分析泄漏，含边信道分析攻击对策的设计中的时间复制可减轻故障注入攻击。通过测量验证了专用集成电路测试芯片（包括各种卡利纳设计）的功能。
英文摘要
The Kalyna block cipher is a Ukrainian cryptography standard, selected through a national competition held between 2007 and 2010 and approved in 2015. Although its software implementations have been introduced, hardware-efficient implementations of the algorithm, i.e., accelerators, do not exist. In this paper, we explore various design architectures to implement its encryption, decryption, and unified encryption/decryption functions, considering the trade-off between area and latency. We present hardware reduction techniques and introduce alternative designs with low area, latency, and energy consumption, targeting an application-specific integrated circuit (ASIC). We present hardware-efficient designs that include countermeasures against side-channel analysis (SCA) and fault injection (FI) attacks, such as hiding, masking, and duplication techniques. We validate these implementations in a 65\;nm ASIC chip. Experimental results confirm the need for alternative designs that explore the design search space for different requirements. The proposed architectures enable hiding the power SCA leakage by randomizing the execution of operations, and the temporal duplication in designs with countermeasures against the SCA attacks can mitigate the FI attacks. The functionality of the ASIC test chip, including various Kalyna designs, is validated through measurements.
