AI 中文总结
本文提出结合非凸与凸优化的多阶段固定轮廓芯片布局规划框架，先通过二次布局生成初始配置，再用基于Adam的投影梯度法解决非凸优化，最后利用对数变换模型消除残余重叠，实验表明该框架线长质量达最优。
AI 中文摘要
布局规划是超大规模集成电路物理设计的关键早期阶段，其质量直接影响互连线长、芯片性能和下游设计效率。本文提出了一个结合非凸和凸优化的多阶段固定轮廓布局规划框架。该框架分三个连续阶段运行。在初始布局规划阶段，二次布局优化模块连接性以生成具有强网络聚类的拓扑感知起始配置，尽管存在显著的模块重叠。在全局布局规划阶段，采用基于Adam的投影梯度法解决非凸优化问题，以最小化线长和重叠。在合法化阶段，利用水平和垂直约束图的对数变换模型在凸公式下消除残余重叠。在MCNC、GSRC和HB+基准测试上的实验表明，该框架实现了当前最优的线长质量，与测试基准上的当前最优布局规划器相比，平均半周长线长至少降低了1%和5%。
英文摘要
Floorplanning is a critical early stage of VLSI physical design, and its quality directly impacts interconnect wirelength, chip performance, and downstream design efficiency. This article presents a multi-stage fixed-outline floorplanning framework that combines non-convex and convex optimization. The framework operates in three successive phases. In the initial floorplanning phase, a quadratic placement optimizes module connectivity to produce a topology-aware starting configuration with strong net clustering, albeit with significant module overlaps. In the global floorplanning phase, Adam-based projected gradient method is employed to solve non-convex optimization that minimizes wirelength and overlap. In the legalization phase, a log-transformed model exploiting horizontal and vertical constraint graphs eliminates residual overlaps under a convex formulation. Experiments on the MCNC, GSRC and HB+ benchmarks demonstrate that the framework achieves state-of-the-art wirelength quality, reducing average HPWL by at least 1\% and 5\% compared to state-of-the-art floorplanners on tested benchmarks.
