AI 中文总结
研究针对概率伊辛机在密集问题上的局限，提出资源高效的流水线式现场可编程门阵列架构，结合深度流水线概率比特更新路径与带宽感知内存组织，提升更新率，改善时间-面积权衡，经验证在组合优化等方面效果显著，为密集优化问题提供可扩展数字概率计算途径。
AI 中文摘要
基于概率比特的概率伊辛机（PIMs）为解决组合优化问题提供了硬件友好途径，但多数数字实现利用稀疏交互实现高吞吐量，限制了其在密集问题上的适用性，内存带宽和数据移动成主要瓶颈。本文展示了一种资源高效的流水线式现场可编程门阵列架构，能实现全连接 PIMs 的高吞吐量执行，同时保持可扩展性和模块化。该架构设计结合深度流水线（>20 阶段）概率比特更新路径与带宽感知片上内存组织。支持不同参数的多种 p 比特数，运行频率高达 300MHz。在固定并行度下，更新率比优化的非流水线基线高一个数量级，在密集工作负载下改善了时间-面积权衡。通过组合优化和低密度奇偶校验解码验证，与软件参考结果高度一致，相对于非流水线设计大幅减少求解时间，确立了流水线作为密集优化问题可扩展数字概率计算的有效途径。
英文摘要
Probabilistic Ising machines (PIMs) based on probabilistic bits offer a hardware-friendly route to solve combinatorial optimization problems, but most digital implementations achieve high throughput by exploiting sparse interactions. This limits their applicability to dense problems, for which memory bandwidth and data movement become the dominant bottlenecks. Here, we show a resource-efficient pipelined Field-Programmable Gate Array architecture enabling high-throughput execution of fully-connected PIMs while maintaining scalability and modularity. This architecture design combines a deeply pipelined (>20 stages) probabilistic bit update path, which overlaps spin evaluation and local-field updates, with a bandwidth-aware on-chip memory organization for the coupling and bias matrices. The architecture supports 512 p-bits with 16-bit fixed-point coefficients and 1024 and 2048 p-bits with 10-bit and 2-bit coefficients, respectively, and operates at up to 300 MHz. At fixed degree of parallelization, it delivers an order-of-magnitude higher update rate than an optimized non-pipelined baseline, while improving the time-area trade-off for dense workloads. Validation on portfolio optimization and low-density parity-check decoding shows close agreement with software references and substantial reductions in time-to-solution relative to the non-pipelined design, establishing pipelining as an effective route to scalable digital probabilistic computing for dense optimization problems.
