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用于先进X射线成像卫星(AXIS)的高速FPGA读出系统

The High-Speed FPGA Readout System for the Advanced X-ray Imaging Satellite (AXIS)

Declan O'Neill, Jill Juneau, Peter Orel, Sven Herrmann, Gregory Prigozhin, Eric D. Miller, Steven W. Allen, Marshall W. Bautz, Tanmoy Chattopadhyay, Kevan Donlon, Robert Goeke, Catherine E. Grant, Beverly LaMarr, Christopher Leitz, R. Glenn Morris, Abigail Y. Pan, Tonya L. Peshel, Artem Poliszczuk, Haley R. Stueber, Keith Warner

arXiv 2607.20380首次发表:更新:

AI 中文总结

介绍用于AXIS卫星的高速FPGA读出系统,该系统对探测器CCD通道高速并行读出,经放大、数字化处理后通过以太网传输到后端,实现每秒20帧读出性能,为未来高通量X射线天文台提供框架。

AI 中文摘要

先进X射线成像卫星(AXIS)是一个探测器级任务概念,旨在实现角秒级空间分辨率以及0.3 - 10 keV波段的高灵敏度光谱成像。斯坦福大学的X射线天文学与观测宇宙学(XOC)小组与麻省理工学院卡夫利研究所(MKI)和麻省理工学院林肯实验室(MIT - LL)合作,正在开发AXIS X射线相机,包括探测器和前端读出电子设备。其焦平面探测器由MIT - LL开发的四个1440x1440像素电荷耦合器件(CCD)组成,每个有16个并行输出通道,通过斯坦福开发的多通道读出芯片(MCRC)放大,再数字化处理构建像素阵列。本文介绍了为实现这些CCD通道高速并行读出而开发的现场可编程门阵列(FPGA)架构,该FPGA以50 MHz采样16个模数转换器(ADC)通道,对像素数据预处理后通过1 Gb以太网链路经用户数据报协议(UDP)传输到后端系统进行事件重建。设计展示了AXIS目标读出性能(每秒20帧)并为未来高通量X射线天文台提供了框架。

英文摘要

The Advanced X-ray Imaging Satellite (AXIS) is a Probe-class mission concept designed to deliver arcsecond spatial resolution, high-sensitivity spectral imaging across the 0.3-10 keV band. The X-ray Astronomy and Observational Cosmology (XOC) Group at Stanford, in collaboration with the MIT Kavli Institute (MKI) and MIT Lincoln Laboratory (MIT-LL), is developing the AXIS X-ray camera, including both the detector and the front-end readout electronics required to meet the mission's demanding performance goals. The telescope's focal plane detector consists of four 1440x1440 pixel charge-coupled devices (CCDs) developed by MIT-LL, each featuring 16 parallel output channels. These outputs are amplified by a high-speed, low-power, low-noise application-specific integrated circuit (ASIC) - the Multi-Channel Readout Chip (MCRC) - developed at Stanford. Following amplification, the analog signals are digitized and processed to construct a pixel array, prior to event detection. Here, we present the field-programmable gate array (FPGA) architecture developed to enable high-speed, parallelized readout of these CCD channels. The FPGA samples 16 analog-to-digital converter (ADC) channels at 50 MHz, performs preprocessing of pixel data, which is then streamed via User Datagram Protocol (UDP) over a 1 Gb Ethernet link to the back-end system for event reconstruction. Our design demonstrates the goal readout performance for AXIS (20 frames per second) and provides a framework for future high-throughput X-ray observatories.

Comments6 pages, 4 figures, to appear in SPIE Astronomical Telescopes + Instrumentation 2026 proceedings

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