AI 中文总结
研究基于小芯片的人工智能片上系统中芯片筛选问题，将KGD到KGRD筛选转变为约束推理问题，提出贝叶斯概率风险模型等四项贡献，蒙特卡罗模拟验证了理论特性及安全保证。
AI 中文摘要
基于小芯片的人工智能片上系统（SoC）的快速发展暴露了半导体测试方法中的一个基本差距。现有的已知良好芯片（KGD）筛选可确保预组装功能正确性，但无法提供组装后可靠性寿命的概率保证。为解决这一限制，本工作将从KGD到已知良好可靠芯片（KGRD）筛选的转变形式化为不完全预组装可观测性上的约束推理问题。在此基础上，提出了四项相互关联的贡献：（i）一个贝叶斯概率风险模型，将预组装遥测映射到具有量化可观测性偏差界限的组装后故障可能性；（ii）一个安全门控决策架构，提供可证明的组装后故障概率保证；（iii）从贝叶斯最优决策理论导出的不确定性感知处置边界；（iv）一个约束闭环反馈机制，在不违反可靠性约束的情况下实现一致的模型改进。对N = 4000个合成芯片的蒙特卡罗模拟研究验证了所有四个理论特性，并确认安全保证在整个测试门限范围内均匀成立。
英文摘要
The rapid growth of chiplet-based artificial intelligence systems-on-chip (SoCs) has exposed a fundamental gap in semiconductor test methodology. Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of post-assembly reliability lifetime. To address this limitation, the present work formalizes the transition from KGD to Known Good Reliable Die (KGRD) screening as a constrained inference problem over incomplete pre-assembly observability. Building upon this formulation, four interlocking contributions are presented: (i) a Bayesian probabilistic risk model that maps pre-assembly telemetry to post-assembly failure likelihood with a quantified observability bias bound; (ii) a safety-gated decision architecture that provides a provable post-assembly failure probability guarantee; (iii) uncertainty-aware disposition boundaries derived from Bayes-optimal decision theory; and (iv) a constrained closed-loop feedback mechanism that delivers consistent model improvement without violating reliability constraints. A Monte Carlo simulation study on N = 4,000 synthetic dies verifies all four theoretical properties and confirms that the safety guarantee holds uniformly across the full range of tested gate threshold.
