重新审视硬件优先级队列架构
Revisiting Hardware Priority Queue Architectures
AI总结：
本文针对硬件优先级队列面临的基础架构相关性存疑及缺乏不同架构全面比较的问题，在现代FPGA平台上实现并评估多种代表性架构，提供定量分析以指导未来设计，填补研究空白。
AI中文摘要：
优先级队列是一种基于优先级而非插入顺序来服务元素的数据结构，在操作系统、图算法和数据压缩等众多应用中至关重要。软件实现通常基于具有O(log N)复杂度的二叉堆，在许多场景中已足够，但在网络和机器人等对延迟敏感的领域可能成为性能瓶颈。基于硬件的优先级队列利用并行性显著降低操作延迟。尽管之前对硬件优先级队列有诸多研究，但仍存在两个主要挑战：许多基础架构多年前提出，其与现代硬件进步的相关性存疑；缺乏不同架构的全面比较。本文通过在现代FPGA平台上实现和评估几种代表性硬件优先级队列架构，并提供定量分析来指导未来设计选择，填补了这两个空白。所有实现、测试和分析可通过我们的开源库获取。
英文摘要：
Priority queues - data structures that serve elements based on priority rather than insertion order - are fundamental in a wide range of applications, including operating systems, graph algorithms, and data compression. Software implementations, typically based on binary heaps with O(log N) complexity, are sufficient for many scenarios; however they can become performance bottlenecks in latency-sensitive domains such as networking and robotics. Hardware-based priority queues exploit parallelism to significantly reduce operation latency, delivering critical performance improvements in latency-sensitive applications. Despite the breadth of prior work on hardware priority queues, two major challenges remain. First, many foundational architectures were proposed and studied years ago, calling into question their relevance given modern hardware advancements. Second, comprehensive comparisons across different architectures are lacking, making it difficult to evaluate trade-offs in performance, resource utilization, and scalability. This paper addresses both gaps by implementing and evaluating several representative hardware priority queue architectures on modern FPGA platforms and providing a quantitative analysis to guide future design choices. All implementations, tests, and analyses are available through our open-source library at https://github.com/realise-lab/hwpq.
