AI 中文总结
研究利用大语言模型从自然语言规范生成RTL设计时的问题，提出VeriRefine方法，将规范细化为明确描述并审核，生成代码后分类修复模拟失败，提升功能正确性，使可合成性成为结构属性。
AI 中文摘要
大语言模型可直接从自然语言规范生成寄存器传输级（RTL）设计，但失败大多源于理解而非编码。规范不正式且模糊，模型解释隐含，错误难发现。VeriRefine 将规范细化视为 RTL 生成的可验证阶段，逐步将散文式规范细化为明确的、受模式约束的设计意图描述，经多层审核修复解释错误，生成代码后对模拟失败分类并针对性修复，使可合成性成为流水线的结构属性。在Claude Sonnet 4.6上，VeriRefine在RTLLM v2.0上功能正确性达94.0%，在VerilogEval-Human v2上达98.1%。
英文摘要
Large language models can generate register-transfer-level (RTL) designs directly from natural language specifications. Their failures, however, arise mostly from understanding rather than coding \cite{zhang2026understanding, qiu2025towards}. A specification is informal and ambiguous, the model's interpretation stays implicit, and every misreading is committed silently into Verilog, where only simulation can expose it. Intermediate representations make the interpretation partly explicit, yet existing works don't verify the interpretation against the specification, and repair simulation failures at the code level regardless of where the misreading originated. VeriRefine instead treats specification refinement as a verifiable stage of RTL generation. It progressively refines the prose specification into an explicit, schema-constrained account of design intent, expressed as per-signal Abstract Signal Transition Functions (ASTFs) that commit each signal's logic style, clock domain, and reset behavior before any code exists and ground every behavior in a verbatim specification sentence. The refined specification then passes a five-layer audit spanning soundness, completeness, consistency, FSM integrity, and core RTL design rules, so interpretation errors are repaired at the representation level before any Verilog is generated. Once code is generated, each simulation failure is classified as an understanding error or a coding error and routed back to the corresponding stage for targeted repair. Because every signal's hardware class is fixed during refinement, synthesizability becomes a structural property of the pipeline rather than a post-hoc check. With Claude Sonnet 4.6, VeriRefine reaches 94.0\% functional correctness on RTLLM v2.0 and 98.1\% on VerilogEval-Human v2.
