发表机构
The University of Winnipeg; University of Manitoba; University of Calgary（温尼伯大学; 曼尼托巴大学; 卡尔加里大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
研究边缘设备上低延迟脑电图分类问题，提出可微逻辑门网络Diff-Logic，通过实验将其与MLP、BNN比较，结果表明Diff-Logic在痴呆筛查中表现优，推理时间稳定，确立其为资源受限脑机接口实用范式。
AI 中文摘要
边缘设备上的实时脑电图分类受传统神经网络浮点运算的限制。我们研究了可微逻辑门网络（Diff-Logic），它可将模型编译为通过按位CPU操作执行的纯布尔电路。通过在跨越两个分类任务（二元痴呆检测和3类情感识别）的四个脑电图数据集上进行严格的等参数实验，我们在四个复杂度级别（50k - 500k参数）将Diff-Logic与匹配容量的多层感知器（MLP）和二值化神经网络（BNN）基线进行比较。在痴呆筛查中，Diff-Logic的宏F1达到80.2%，比MLP基线高6.8%。在情感识别中，MLP保持适度性能优势，但在功率受限（7W）的英伟达Jetson Orin Nano CPU（单核）上部署时，延迟高2.3倍，模型大小大14倍。关键的是，Diff-Logic推理时间在模型规模增加10倍时几乎保持不变，在最大复杂度级别比MLP实现了2.9倍的峰值加速。我们的结果确立了基于逻辑的神经架构作为资源受限脑机接口的实用范式，在满足便携式边缘部署的延迟和内存限制的同时，实现了有竞争力或更优的性能。代码可在GitHub上获取：此https URL
英文摘要
Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3$\times$ higher latency and 14$\times$ larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10$\times$ increase in model scale, achieving a peak speedup of 2.9$\times$ over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic
CommentsPublished in the Proceedings of the 39th Canadian Conference on Artificial Intelligence, PMLR 318, pages 377-391, 2026. Conference version: https://proceedings.mlr.press/v318/dharia26a.html
Journal refProceedings of the 39th Canadian Conference on Artificial Intelligence, PMLR 318:377-391, 2026
