发表机构
UC Berkeley; Sony（加州大学伯克利分校; 索尼公司）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
研究移动设备低电压下NPU推理因编译器融合致功率突发问题，提出测量引导的预编译图重写方法，可减少峰值电流、降低延迟开销、保持稳定延迟并偏移DVFS裕度。
AI 中文摘要
移动设备越来越依赖实时NPU推理处理相机和感知工作负载。然而，在低电压条件下，单次推理会在供电网络中引起瞬时电压降，导致电源管理集成电路调用动态电压和频率缩放（DVFS）并增加延迟。我们对一款商用智能手机上的这种影响进行了测量研究。我们发现移动NPU编译器中的激进算子融合会创建单片超层，其集中执行会产生大的峰值电流突发。这些突发会使DVFS启动电压向上移动并减小低电压工作裕度。我们进一步评估了一种实用的黑盒缓解方法：一种测量引导的预编译图重写，在选定的峰均功率比热点处插入屏障，以防止供应商NPU编译器中有害的超层合并。在骁龙8 Gen 3上，对于分辨率为768 x 768的ImageNet-1k上的MobileNetV4，该方法将峰值电流从3.12 A降至1.94 A，延迟开销为3.76%，在更低电压状态下保持稳定延迟，并使推断的DVFS裕度偏移约173 mV。
英文摘要
Mobile devices increasingly rely on real-time NPU inference for camera and perception workloads. Under low-voltage conditions, however, a single inference can induce an instantaneous voltage droop in the power-delivery network, causing the power management integrated circuit to invoke dynamic voltage and frequency scaling (DVFS) and increase latency. We present a measurement study of this effect on a commercial smartphone. We show that aggressive operator fusion in a mobile NPU compiler can create monolithic superlayers whose concentrated execution produces large peak-current bursts. These bursts shift the DVFS-onset voltage upward and reduce the low-voltage operating margin. We further evaluate a practical black-box mitigation: a measurement-guided, pre-compilation graph rewrite that inserts barriers at selected peak-to-average power ratio hot spots to prevent harmful superlayer merging in the vendor NPU compiler. On Snapdragon 8 Gen 3 with MobileNetV4 at 768 x 768 resolution on ImageNet-1k, this method reduces peak current from 3.12 A to 1.94 A with 3.76% latency overhead, preserves stable latency deeper into the low-voltage regime, and shifts the inferred DVFS margin by approximately 173 mV.
Comments16 pages, 6 figures
