AI 中文总结
研究如何在量子LDPC码中快速进行逻辑运算，提出仅用猫态的方法，设计联合测量协议及调度器码，经数值模拟，该方法在测量可交换逻辑算子、随机克利福德电路及非克利福德门时均有显著加速。
AI 中文摘要
量子LPDC码因其高编码率，与表面码相比，在容错量子计算中所需的量子比特开销大幅减少。然而，对同一块中编码的多个逻辑量子比特同时进行操作更具挑战性，可能会减慢逻辑运算速度。先前工作通过设计复杂资源态在LDPC码中执行逻辑测量来解决此问题。本文提出一种仅消耗猫态的方法。以往基于猫态的测量专注于单个逻辑测量，而本文设计了一个用于联合测量\(\ell\)个可交换逻辑算子的协议。关键要素是设计一个调度器码来确定测量序列并允许对所有逻辑测量结果进行解码。对行走猫架构的LDPC码Q70和Q102的数值模拟表明，对于\(\ell = 20\)个可交换逻辑算子的测量，比维特比测量快近\(3\)倍。将快速逻辑测量与CliNR部分纠错方案的新变体相结合，对于随机克利福德电路，加速比高达\(74\)倍。该方法也适用于非克利福德门，对于托佛利门加速比高达\(5\)倍。
英文摘要
Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of $\ell$ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly $3\times$ over Viterbi measurements for the measurement of $\ell=20$ commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed-up of up to $74\times$ for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed-up of up to $5\times$ for Toffoli gates.
Comments14 pages, 4 figures
