AI 中文总结
该研究提出开源工具，从高级规范自动生成高效硬件解析器。利用PIR解耦前端与后端，扩展模式匹配。通过以太网和网络入侵检测流程演示，生成的解析器在频率和资源利用上表现出色，为多样应用实现高性能、资源高效的硬件解析器。
AI 中文摘要
本文介绍了一种开源工具，可从高级规范自动生成高效硬件解析器。它使用解析中间表示（PIR），将特定应用前端与通用寄存器传输级（RTL）生成后端解耦。后端生成优化的、可读的SystemVerilog，处理有限状态机生成、字节对齐等。该工具还通过引入自定义符号令牌扩展模式匹配。通过以太网协议解析和网络入侵检测的两个端到端流程进行演示，生成的以太网解析器在频率和资源利用上优于先前工作，开源框架助力设计高性能、资源高效的硬件解析器。
英文摘要
This work presents an open-source tool for automatically generating efficient hardware parsers from high-level specifications. It uses a parsing intermediate representation (PIR) that decouples application-specific frontends from a common register-transfer level (RTL) generation backend. The backend produces optimized, human-readable SystemVerilog, handling FSM generation, byte-alignment, and multi-cycle field straddling for arbitrary datapath widths. The tool also extends pattern matching beyond simple equality checks by introducing custom symbolic tokens to support operations that existing parser generators cannot express, such as range validation, negation, and comparisons against external ports. We demonstrate two end-to-end flows using a P4 frontend for Ethernet protocol parsing and a Snort frontend for network intrusion detection, both using the same unmodified backend. The generated Ethernet parsers achieve up to 226% higher operating frequency and up to 97% fewer FPGA logic resources than prior work. A controlled synthetic study further shows that the tool's hierarchical pattern decomposition yields up to 8x resource utilization reduction over monolithic designs. Our open-source framework enables designers to rapidly implement high-performance, resource-efficient, vendor-agnostic hardware parsers for diverse applications.
