发表机构
Hong Kong University of Science and Technology (HKUST)（香港理工大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
针对RTL精确时序预测难题，现有基于图的方法存在局限。RTL-Sequencer提出基于序列的范式，通过线性化逻辑锥、应用序列模型及定制协同技术实现可扩展预测，实验证明其相比基线有显著改进，推动早期时序优化。
AI 中文摘要
寄存器传输级（RTL）的精确时序预测是设计自动化中一项长期存在的挑战。现有的基于图的方法存在感受野有限、复杂度高和缺乏信号方向性等问题。我们提出了RTL-Sequencer，这是一种新颖的基于序列的范式，通过广度优先遍历线性化逻辑锥并应用现代线性序列模型来实现可扩展的RTL时序预测。此外，序列模型通过序列洗牌、双向建模、可微建模和混合图序列架构这四种协同技术进行定制。大量实验表明，RTL-Sequencer比现有基线有显著改进，推动了早期时序优化。
英文摘要
Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models. Furthermore, sequence models are customized by four synergistic techniques, including sequence shuffling, bidirectional modeling, differentiable modeling, and a hybrid graph-sequence architecture. Extensive experiments demonstrate significant improvements of RTL-Sequencer over state-of-the-art baselines, advancing early-stage timing optimization.
CommentsAccepted by Design Automation Conference (DAC) 2026
