AI 中文总结
研究在三价平面架构中创建逻辑纠缠，通过引入可扩展电路结构实现格手术，与四价方案比减少资源，经实验模拟基准测试逻辑保真度，为可扩展平面三价量子比特架构承载逻辑量子处理器开辟道路。
AI 中文摘要
低开销量子纠错方案对于在包含多个逻辑量子比特的寄存器上进行量子计算至关重要。对于最近邻量子比特连接性有限的平面架构，表面码已成为主导范例。近期理论和实验表明三价物理量子比特连接性足以实现容错量子纠错。本文在此三价架构背景下研究格手术，并引入可扩展电路结构来实现它。与四价测量方案相比，三价格手术协议在总计\(\mathcal{O}(d^2)\)个量子比特中减少了\(\mathcal{O}(d)\)个所需资源，在总计\(\mathcal{O}(d^3)\)个双量子比特门中减少了\(\mathcal{O}(d)\)个。通过针对基于磁通量子比特架构的实验现实模拟对两种格手术方案的逻辑保真度进行基准测试，发现距离为三时潜在改进高达约\(25\%\)。这些结果为可扩展平面三价量子比特架构承载基于表面码的逻辑量子处理器开辟了道路。
英文摘要
Low-overhead quantum error-correction schemes are essential for enabling quantum computation on registers containing multiple logical qubits. For planar architectures with limited nearest-neighbor qubit connectivity, the surface code has emerged as the leading paradigm. Recent theoretical and experimental work has shown that a physical-qubit connectivity of degree three is sufficient to implement fault-tolerant quantum error correction. In this work, we study lattice surgery in the context of such trivalent architectures and introduce scalable circuit constructions to implement it. Compared with the four-valent measurement scheme, the trivalent lattice-surgery protocol reduces the required resources by $\mathcal{O}(d)$ qubits out of a total qubit count of $\mathcal{O}(d^2)$ and by $\mathcal{O}(d)$ two-qubit gates out of a total two-qubit gate count of $\mathcal{O}(d^3)$. We benchmark the logical fidelity of both lattice-surgery schemes in terms of experimentally realistic simulations targeting an implementation with a fluxonium qubit based architecture and find a potential improvement of up to $\approx25\%$ for distance-three. These results open a way for scalable planar trivalent qubit architectures to host a surface-code-based logical quantum processor.
