AI 中文总结
针对先进封装布线难题，提出可微布线驱动的布局规划与引脚分配算法。含线长最小化、交叉感知引脚分配、布线最大化方法，经实验，该方法实现100%可布线性，相比领先方法，特定情况下线长最多降约23%。
AI 中文摘要
随着先进封装技术的发展，再分布层（RDL）中互连密度的增加使得布线对封装布局规划至关重要。同时，功率完整性要求常常为电源传输网络（PDN）预留扇入区域，迫使信号网络通过扇出区域，使布线估计变得复杂。现有的基于均匀网格的拥塞模型无法准确表征扇出拥塞，而先前的引脚分配方法难以评估网络交叉。我们提出了一种用于具有扇出路由的先进封装的可微布线驱动的布局规划和引脚分配算法。首先，一种可微线长最小化方法直接对离散芯片方向进行建模，并将线长梯度反向传播到芯片位置和方向。它在固定引脚选择下减少线长，同时避免连续角度建模的偏差。其次，一种交叉感知引脚分配方法将网络交叉成本纳入多策略DPSO算法，并使用GPU并行成本评估来有效减少线长。最后，一种可微布线最大化方法构建了一个针对扇出路由的拥塞模型，并建立了从拥塞信息到芯片位置的反向传播路径，从而指导布线优化。实验结果表明，我们的方法在所有基准测试中实现了100%的可布线性。对于基线成功布线的情况，与配备我们引脚分配流程的领先布局规划方法相比，它最多可将线长减少约23%。
英文摘要
As advanced packaging technology evolves, increasing interconnect density in redistribution layers (RDLs) makes routability critical to package floorplanning. Meanwhile, power integrity requirements often reserve fan-in regions for the power delivery network (PDN), forcing signal nets through fan-out regions and complicating routability estimation. Existing uniform grid-based congestion models cannot accurately characterize fan-out congestion, while previous pin assignment methods struggle to evaluate net crossings. We propose a differentiable routability-driven floorplanning and pin assignment algorithm for advanced packaging with fan-out routing. First, a differentiable wirelength minimization method directly models discrete chip orientations and back-propagates wirelength gradients to chip locations and orientations. It reduces wirelength under fixed pin selection while avoiding the bias of continuous-angle modeling. Second, a crossing-aware pin assignment method incorporates net-crossing cost into a multi-strategy DPSO algorithm and uses GPU-parallel cost evaluation to reduce wirelength efficiently. Finally, a differentiable routability maximization method constructs a congestion model tailored to fan-out routing and establishes a back-propagation path from congestion information to chip locations, thereby guiding routability optimization. Experimental results show that our method achieves 100% routability on all benchmarks. For cases successfully routed by the baselines, it reduces wirelength by up to approximately 23% compared with a leading floorplanning method equipped with our pin assignment flow.
