AI 中文总结
为4DPHOTON项目中Timepix4 ASIC设计实现灵活数据采集系统，采用模块化FPGA架构，结合高速读出、以太网传输和多板同步，支持零背压操作，适应不同条件，多系统同步精度高，可用于探测器表征等，介绍了相关设计与性能。
AI 中文摘要
本文介绍了为4DPHOTON项目中的Timepix4 ASIC开发的灵活数据采集系统的设计与实现。该系统基于模块化的以FPGA为中心的架构，结合高速串行读出、基于以太网的数据传输和确定性多板同步。硬件平台包括由商业FPGA载板等组成的可扩展堆栈，固件架构分离控制和数据路径。设计支持对ASIC的零背压操作，能适应不同实验条件，多DAQ系统通过公共时钟和触发分配网络同步，精度达亚100 ps。该系统已开发用于支持4DPHOTON探测器概念的探测器表征等，还介绍了硬件组织等方面内容。
英文摘要
This paper presents the design and implementation of a flexible data acquisition system13 developed for the Timepix4 ASIC. The system is based on a modular14 FPGA-centric architecture combining high-speed serial readout, Ethernet-based data transport,15 and deterministic multi-board synchronization. The hardware platform includes a scalable stack16 composed of commercial FPGA carrier boards, FMC-based interface electronics, detector-specific17 chipboards, and a dedicated Trigger Logic Unit for synchronized operation.18 The firmware architecture separates control and data paths, enabling independent configuration19 and high-throughput acquisition through UDP over 10 GbE links. The design supports zero-back-20 pressure operation toward the ASIC and allows adaptation of the readout bandwidth to different21 experimental conditions. Synchronization between multiple DAQ systems is achieved through22 a common clock and trigger distribution network, experimentally demonstrated with sub-100 ps23 precision.24 The system has been developed to support detector characterization, laboratory measurements,25 and beam-test campaigns for the 4DPHOTON detector concept. Hardware organization, firmware26 architecture, synchronization strategy, and performance measurements are presented.
Comments18 pages, 8 figures
