AI 中文总结
研究混合量子-经典系统性能受经典控制等因素限制的问题，提出HybridQC模拟器，通过将HCU建模为可配置图、分解作业并校准测量，可评估混合架构多方面限制，为其性能评估提供系统框架。
AI 中文摘要
混合量子-经典应用性能越来越受经典控制、主机到量子处理单元（QPU）通信和调度的限制，而非量子执行。现有模拟器和运行时接口无法解决系统拓扑问题。本文介绍HybridQC，一种用于紧密耦合混合计算单元（HCU）的拓扑感知离散事件模拟器。它将HCU建模为可配置图，分解作业为阶段的有向无环图，在可互换调度策略下执行。通过来自D-Wave和IBM处理器的实时测量校准，区分物理QPU占用和云时钟延迟。模型对D-Wave QPU访问时间的平均绝对百分比误差为3.92%-8.04%，对IBM量子秒测量为5.26%-19.01%。工作负载实验表明，平衡的10倍HCU扩展对完工时间的改善有限，改变调度策略影响更大，且扩展性因工作负载维度而异。HybridQC为评估混合架构的拓扑、调度和扩展限制提供了系统框架。
英文摘要
Hybrid quantum-classical application performance is increasingly limited by classical control, host-to-QPU communication, and scheduling rather than quantum execution. Existing simulators and runtime interfaces analyze individual kernels but fail to address system-topology questions, such as controller bottlenecks, diminishing returns of QPU capacity, or resource contention under heterogeneous workloads. We introduce HybridQC, a topology-aware discrete-event simulator for tightly coupled hybrid compute units (HCUs). HybridQC models HCUs as configurable graphs of classical processors, memory, controllers, quantum annealing (QA) and digital quantum computing (DQC) devices, and communication links. It decomposes jobs into typed, directed acyclic graphs of stages, ranging from input preparation to classical postprocessing, executed under interchangeable scheduling policies. Calibrated with live measurements from D-Wave (Advantage 1 and 2) and IBM (Kingston, Marrakesh, and Fez) processors, HybridQC distinguishes physical QPU occupancy from cloud wall-clock latency. The models achieve mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds measurements. Workload experiments reveal that a balanced 10x HCU scaling improves makespan by only 2.19x-3.42x, while altering scheduling policies shifts makespan by up to 1.80x for a 20-job workload. Scalability varies heavily by workload dimension: a 100x input data increase yields a 306 s median runtime, whereas a 100x joint increase in circuit count, shot count, and circuit depth drives runtime to 4.806x10^7 s on an unchanged HCU. HybridQC offers a systematic framework for evaluating the topology, scheduling, and scaling limits of hybrid architectures prior to physical deployment.
