发表机构
University of California, Riverside（加州大学河滨分校）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
研究针对现有架构模拟器不足，提出Microflow框架，将执行跟踪转换为MFIR以捕获多元素依赖关系，实现从停顿追溯根本原因，能精确归因、揭示现象、分解关键路径，为性能分析和软硬件协同设计提供基础，通过SPEC CPU 2017基准测试发现隐藏瓶颈。
AI 中文摘要
现有架构模拟器仅展示聚合指标或原始跟踪，无法揭示微架构事件间复杂交互及其与程序执行的关系。因此，架构师只能观察性能症状，却无法跨抽象层系统地找出根本原因。本文介绍了Microflow，一个将因果关系提升为一流分析对象的可观测性框架。它将执行跟踪转换为Microflow中间表示（MFIR），明确捕获软件语义、指令、微架构事件和硬件资源之间的依赖关系。通过统一这些元素，MFIR实现了从观察到的停顿直接追溯其根本原因，为自动根本原因分析铺平了道路。Microflow精确地归因停顿，揭示不可观测现象，并通过反事实分析实现精确的关键路径分解。这些能力使得对现有工具无法处理的复杂软硬件交互进行系统推理成为可能。使因果关系可查询，Microflow为性能分析和软硬件协同设计提供了坚实基础。我们在两个SPEC CPU 2017基准测试中进行了演示，发现了聚合症状中不可见的瓶颈：leela中隐藏的预测错误成本和mcf中的跨循环迭代争用。
英文摘要
Modern computer architecture relies heavily on simulation to identify bottlenecks and evaluate optimizations. However, existing microarchitectural performance analysis methods are fundamentally limited by an instruction-centric paradigm that captures only downstream symptoms while leaving the true microarchitectural root cause opaque. Because modern processors are governed by complex interactions across non-instruction entities like prefetchers, replacement policies, and shared queue occupancies, instruction-centric frameworks miss the mechanisms that dictate performance. To eliminate this blind spot, we present Microflow, a framework that achieves causal observability in microarchitectural simulation. To address this, we introduce the Microflow intermediate representation (MFIR), which models execution through microarchitecture-tailored core abstractions such as flows, resource tenancies, and causal edges. By compiling simulation runs into a relational causal database, Microflow decouples tracing from analytical processing. This transforms complex diagnostics into expressive queries, enabling architects to trace performance symptoms directly to hardware root causes without developing bespoke analysis scripts or running costly re-simulations for every new question. We demonstrate that Microflow solves pathologies opaque to conventional tools. Across CVP-1 benchmarks, Microflow decomposes a 22% prefetcher oracle headroom by attributing 61.4% of stall mass to specific hardware prefetcher decisions, yielding a 2.31% average speedup (peaking at 25.11%). Furthermore, it exposes the hidden pipeline-blocking residue of wrong-path execution with high portability and precision across simulators.
