ChipVerilog：一个用于基于大语言模型的Verilog RTL生成的大规模、源自OpenCores的基准测试
ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation
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中文总结 AI 辅助
研究基于大语言模型的Verilog RTL生成，提出ChipVerilog基准测试，它源自OpenCores IP/核心设计，含64个生成目标，涵盖多种设计家族，能体现实际代码规模等，经多种方式验证生成的RTL，揭示大规模RTL生成有挑战。
中文摘要 AI 辅助
大语言模型在Verilog RTL生成方面展现出强大潜力。然而，现有的许多基准测试是基于简短、独立的模块级任务构建的，无法完全涵盖实际IP和处理器核心RTL中的代码规模、层次结构和模块交互。我们提出了ChipVerilog，这是一个基于OpenCores IP/核心设计构建的从描述到Verilog生成的基准测试。该基准测试包含来自五个设计家族的64个生成目标，有单模块目标和跨模块目标，一些目标超过1000行Verilog代码。每个基准测试实例由一对规范文档和参考RTL构建而成。生成的RTL通过编译检查，并通过等价性检查或模拟进行验证。结果表明大规模RTL生成仍具有挑战性，尤其是对于分层和跨模块设计。
英文摘要
Large language models have shown strong potential for Verilog RTL generation. However, many existing benchmarks are built from short, self-contained module-level tasks. These tasks are useful for controlled evaluation, but they do not fully capture the code scale, hierarchy, and module interactions found in practical IP and processor-core RTL. We present ChipVerilog, a description-to-Verilog generation benchmark built from OpenCores IP/core designs. The benchmark contains 64 generation targets from five design families: OR1200, double-precision FPU, MIPS-16, I2C, and CORDIC. It includes both single-module targets and cross-module targets that instantiate or interact with other RTL modules. Several targets exceed 1,000 lines of Verilog, making ChipVerilog substantially larger and structurally more complex than typical module-level suites. Each benchmark instance is constructed from a pair of specification documents and reference RTL. We extract the target functionality, write a detailed natural-language description, and manually review the description for correctness and clarity. Generated RTL is checked by compilation and validated through equivalence checking for local modules, or by simulation for integrated IP/core targets. Results show that large-scale RTL remains challenging, especially for hierarchical and cross-module designs.
