CLIP-3D：3D集成电路性能和物理约束的闭环评估
CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs
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中文总结 AI 辅助
研究3D集成电路设计中布局对性能的影响，提出CLIP-3D流程，通过物理块表示和热感知布局规划器，将布局相关效应提前暴露给早期架构探索，共同优化跨层宏分配和面内布局以实现BIPS。
中文摘要 AI 辅助
3D集成在更小的空间内提供了更高的功率，因此候选设计的实际吞吐量取决于其布局。像gem5这样的架构模拟器在理想化的时序下报告IPC，但无法生成决定实际每秒十亿条指令数（BIPS）的每块功耗图、缓存周期数或3D布局。我们提出了CLIP-3D，一种在调用任何签核工具之前，将3D布局驱动的热、布线和缓存效应暴露给早期架构探索的左移流程。第一阶段将架构配置提升为物理块表示，第二阶段在该表示上运行分析性的3D热感知布局规划器，其目标嵌入了一个闭式持续频率表达式，跨层宏分配和面内布局共同优化以实现BIPS。
英文摘要
3D integration packs more power into a smaller footprint, so a candidate design's actual throughput depends on its layout: which macro sits on which tier, where the hot spot lands, and how cache geometry maps to access cycles. Architectural simulators like gem5 report IPC under idealized timing. They do not produce the per-block power map, the cache cycle counts, or the 3D layout that decide the realized billion-instructions-per-second (BIPS), so early-stage 3D-IC exploration selects designs without accounting for the effects that decide whether they throttle on silicon. We present CLIP-3D, a shift-left flow that exposes 3D layout-driven thermal, wire, and cache effects to early-stage architectural exploration before any sign-off tool is invoked. The first stage lifts an architectural configuration into a physical block representation: McPAT for per-block dynamic and leakage power, CACTI for cache geometry and access cycles, and a HotSpot-compatible 3D stack discretization. The second stage runs an analytical 3D thermal-aware floorplanner over that representation. The floorplanner objective embeds a closed-form sustained-frequency expression derived from the linearity of HotSpot's steady-state operator and the standard CMOS power-frequency decomposition. Cross-tier macro assignment and in-plane placement are co-optimized for the realized BIPS rather than for a half-perimeter wirelength (HPWL)-plus-temperature surrogate with hand-tuned weights.
