AI 中文总结
研究逻辑缩放进入埃时代下二维CFET架构，开发特定集成流程并展示关键模块。虽二维全栅环绕CFET有潜力，但受非理想因素限制，其在A2节点无接触多晶硅间距缩放优势。通过多尺度评估框架分析，指出需协同优化多方面及采用二维特定架构来取得进展。
AI 中文摘要
随着逻辑缩放进入埃时代，基于原子级薄二维半导体的垂直堆叠互补场效应晶体管（CFET）为将器件缩放扩展到A2节点之后提供了一条潜在途径。本文开发了一种面向A2的二维CFET集成流程，特征尺寸为36nm，栅长为10nm，并展示了几个关键工艺模块的初步演示。尽管二维全栅环绕CFET具有原子级薄的沟道，但在A2节点，其在接触多晶硅间距缩放方面并不比硅全栅环绕CFET更具优势，因为接触形成的限制导致最小接触多晶硅间距类似，均为36nm。还结合了关键评估与多尺度功率-性能-面积（PPA）评估框架，涵盖量子输运模拟、紧凑模型生成、面向A2的二维CFET全栅环绕（GAA）集成流程定义、寄生参数提取和电路级基准测试。然而，分析表明，二维全栅环绕CFET的预期优势受到非理想因素的强烈限制，特别是高接触电阻和主要的布局引起的寄生电容。尽管架构优化可以提高有效电流/有效电容比，但绝对电容的相应增加限制了电路级的增益。有意义地进展需要对接触、输运和寄生参数进行协同优化，以及二维特定的CFET架构。
英文摘要
As logic scaling enters the angstrom era, vertically stacked complementary field-effect transistors (CFETs) based on atomically thin two-dimensional (2D) semiconductors offer a potential route to extend device scaling beyond the A2 node. Here, we develop an A2-oriented 2D CFET integration flow with a CPP of 36 nm and Lg of 10 nm and present initial demonstrations of several key process modules. Despite their atomically thin channels, 2D GAA CFETs do not provide a contacted poly pitch scaling advantage over Si GAA CFETs at the A2 node, because contact formation constraints impose a similar minimum CPP of 36 nm. We also combine a critical assessment with a multiscale power-performance-area (PPA) evaluation framework spanning quantum transport simulations, compact-model generation, A2-targeted 2D CFET gate-all-around (GAA) integration-flow definition, parasitic extraction and circuit-level benchmarking. Our analysis, however, shows that the expected benefits of 2D GAA CFETs are strongly constrained by non-idealities, in particular high contact resistance and dominant layout-induced parasitic capacitances. Although architectural optimization can improve the Ieff/Ceff ratio, the associated rise in absolute capacitance limits circuit-level gains. Meaningful progress will require co-optimization of contacts, transport and parasitics, together with 2D-specific CFET architectures.
Comments25 pages, 5 figures
