作为双核微控制器上操作系统服务的跨核推理卸载
Cross-Core Inference Offload as an Operating-System Service on Dual-Core Microcontrollers
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中文总结 AI 辅助
研究双核微控制器中跨核推理卸载，将其不对称性用于SynapticOS架构。通过消息服务跨核，用共享SRAM环传输数据，在FRDM - MCXN947上测试，给出性能数据，还报告缺陷及解决方法，展示了该跨核推理卸载方案的有效性。
中文摘要 AI 辅助
双核微控制器是不对称的，如恩智浦的MCXN947，第二个Cortex - M33没有FPU、DSP扩展、TrustZone或MPU。在基于Zephyr的开源运行时SynapticOS的第三阶段双核架构中，将这种不对称视为设计输入：AI运行时（模型、NPU/DSP、调度器）驻留在功能强大的核心上，应用核心仅通过基于消息的操作系统服务（远程系统调用）进行推理。传输是共享SRAM中的一对无锁单生产者/单消费者环：每个索引有一个写入器，32位自由运行计数器，仅通过数据内存屏障排序（该平台没有跨核原子操作）。由于环状态是共享的，重启的应用核心可自行重新加入。请求携带优先级类，错误和超时传播到调用者，张量在共享插槽中进行零拷贝暂存。在FRDM - MCXN947上测量（两个核心均为150 MHz）：应用核心在1514微秒内启动，在2554微秒内完成握手，11次启动中比特相同；往返通常为15微秒/最坏情况为81微秒（预算为50微秒）；推送成本为25个周期；1913次服务两个模型测试无错误。运行时核心上的MPU区域保护应用核心的RAM（故障注入验证）；保护是单向的，应用核心没有MPU，且ARMv8 - M无法阻止特权读取。报告了两个硬件揭示的缺陷：将第二个核心释放到擦除的闪存中会使整个芯片及其调试端口陷入困境（现在通过ROM - API空白检查防止），以及Zephyr闪存驱动Kconfig会静默解除设备树MPU保护（现在在运行时编程）。固件为98.9 KB闪存（运行时核心）和32.4 KB（应用核心，64 KB RAM中的42.6 KB）；13个套件中的108次测试100%通过。遵循Apache 2.0许可：此https URL
英文摘要
Dual-core MCUs are asymmetric: on NXP's MCXN947, the second Cortex-M33 has no FPU, DSP extension, TrustZone, or MPU. We treat the asymmetry as a design input in the Phase 3 dual-core architecture of SynapticOS, an open-source Zephyr-based runtime: the AI runtime (models, NPU/DSP, scheduler) lives on the capable core, and the application core reaches inference only via a message-based OS service -- a remote system call. The transport is a pair of lock-free single-producer/single-consumer rings in shared SRAM: one writer per index, free-running 32-bit counters, ordering by data-memory barriers alone (the platform has no cross-core atomics). Because ring state is shared, a rebooting application core rejoins unaided. Requests carry priority classes, errors and timeouts propagate to the caller, and tensors stage zero-copy in a shared slot -- a 27 KB frame cannot exist twice in 64 KB of RAM. Measured on the FRDM-MCXN947 (both cores 150 MHz): the application core boots in 1,514 us and completes the handshake in 2,554 us, bit-identical over 11 boots; round trips are 15 us typical / 81 us worst-case (50 us budget); pushes cost 25 cycles; a 1,913-serve two-model soak had zero errors (stub-NPU latencies bracket transport, not silicon). An MPU region on the runtime core guards the application core's RAM (fault-injection verified); protection is one-directional -- the application core has no MPU, and ARMv8-M cannot block privileged reads. Two hardware-revealed defects are reported: releasing the second core into erased flash wedges the whole chip and its debug port (now prevented by a ROM-API blank check), and a Zephyr flash-driver Kconfig silently disarmed the devicetree MPU guard (now programmed at runtime). Firmware is 98.9 KB flash (runtime core) and 32.4 KB (application core, 42.6 of 64 KB RAM); 108 tests in 13 suites pass 100%. Apache 2.0: https://github.com/Dimitrios-Kafetzis/SynapticOS
