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arXiv 2607.12118quant-ph

具有缺陷组件的超导量子比特阵列上的纠错

Error correction on an array of superconducting qubits with defective components

Julien M. Drouet, Xanda C. Kolesnikow, Campbell K. McLauchlan, Georgia M. Nixon, Seok-Hyung Lee, Dominic J. Williamson, Stephen D. Bartlett, Benjamin J. Brown, Robin Harper

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中文总结 AI 辅助

研究固态量子计算中含缺陷组件的超导量子比特阵列的纠错问题,通过排除性能不佳组件等策略操作距离为5的表面码,大幅降低逻辑错误概率,证明了缺陷排除方法对固态量子计算扩展的重要作用。

中文摘要 AI 辅助

固态量子计算架构需要制造许多耦合量子比特的阵列。制造过程不可避免地会产生性能各异的量子比特和耦合器,一些组件因制造不完善而性能不佳。量子纠错需要高性能组件,必须处理这些缺陷。本文在由120个超导量子比特的方形晶格阵列组成的量子处理器上实现并比较了操作距离为5的表面码的策略。通过排除性能不佳的组件,与忽略缺陷的标准方法和缺陷感知解码方法相比,在存储实验中逻辑错误概率大幅降低。与标准的忽略缺陷方法相比,排除缺陷时每轮逻辑错误最多有2.8倍的改善。缺陷感知解码收益不大。缺陷对基于测量的逻辑操作也特别有害,排除缺陷可恢复基于测量的逻辑门性能。结合泄漏后选择和缺陷排除策略,逻辑错误进一步大幅减少,实现了距离为5的码在一个基上优于最佳距离为3的码。实验证明了缺陷排除方法在固态量子计算方法扩展中的基本效用。

英文摘要

A solid-state quantum-computing architecture will require the fabrication of arrays of many coupled qubits. It is inevitable that this process will produce qubits and couplers with varying performance, with some components underperforming due to imperfect fabrication. Quantum error-correction requires high-performing components and hence these defects must be dealt with, either by adapting the code to exclude the defects, or by informing the decoder to accommodate defects in post-processing. Here we implement and compare strategies to operate distance-5 surface codes on a quantum processor consisting of a square-lattice array of 120 superconducting qubits. We demonstrate a dramatic reduction in the probability of a logical error in a memory experiment by excluding underperforming components, compared with both a standard approach of ignoring defects, and a defect-aware decoding approach. We observe up to 2.8X improvement in logical errors per round when excluding defects compared with the standard defect-ignorant approach (1.62% compared to 4.49%). In contrast, defect-aware decoding gives only modest gains. Defects are also expected to be particularly harmful for measurement-based logical operations. Using a stability experiment we show that excluding defects resurrects measurement-based logic gate performance, observing a 6.3% per-round suppression of failure rate when excluding defects, compared to zero suppression otherwise. Furthermore, we show a further substantial decrease in logical errors when using leakage post-selection in combination with our defect exclusion strategies, resulting in a distance-5 code outperforming the best distance-3 in one basis. Our experiments therefore give a proof-of-principle demonstration of the essential utility of defect exclusion methods in the scale-up of solid-state quantum computing approaches.

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