AI 中文总结
研究针对AMD Ryzen AI NPU编程难的问题，提出IRONSmith可视化数据流设计环境，用户无需写代码，通过连接代表多种模式的线设计ML应用，后端自动转换为可执行代码并在该NPU上运行，弥合知识与编程差距，助力多类人群。
AI 中文摘要
机器学习推理越来越依赖专用硬件加速器来提高吞吐量和功率效率。诸如AMD Ryzen AI NPU之类的神经处理单元（NPU）在机器学习方面比CPU和GPU具有显著优势，但对其进行编程需要专业的框架知识。我们展示了IRONSmith，这是首个用于对AMD Ryzen AI NPU进行编程的可视化数据流设计环境。IRONSmith提供了一个交互式画布，将AI引擎瓦片网格显示为视觉上相连的块，用户无需编写任何代码，通过连接代表FIFO、拆分/连接模式、广播连接和DDR传输的线来设计机器学习数据流应用程序。计算内核从预构建库中分配，工作函数通过属性面板进行配置。IRONSmith的后端管道会自动将可视化设计转换为可执行的IRON Python，自动处理结构完成、导入解析和依赖管理。生成的代码可直接在AMD Ryzen AI NPU上执行。我们展示了IRONSmith在复杂度不断增加的机器学习设计中的应用，从单瓦片向量直通到多瓦片矩阵运算，再到完整的多层感知器，所有这些都是通过可视化设计并在AMD Ryzen AI NPU上成功执行的。IRONSmith通过弥合机器学习知识与NPU编程专业知识之间的差距，为教育工作者、学生、机器学习研究人员和工程师提供服务，扩大了对这种在消费和企业设备中迅速成为标准的硬件的使用范围。
英文摘要
Machine learning inference increasingly relies on specialized hardware accelerators for throughput and power efficiency. Neural Processing Units (NPUs), such as the AMD Ryzen AI NPU, offer significant ML advantages over CPUs and GPUs, but programming them requires expertise in specialized frameworks. We present IRONSmith, the first visual dataflow design environment for programming AMD Ryzen AI NPUs. IRONSmith provides an interactive canvas displaying the AI Engine tile grid as visually connected blocks, allowing users to design ML dataflow applications by connecting tiles with wires representing FIFOs, split/join patterns, broadcast connections, and DDR transfers without writing any code. Compute kernels are assigned from a pre-built library, and worker functions are configured through property panels. IRONSmith's backend pipeline automatically translates the visual design into executable IRON Python, handling structural completion, import resolution, and dependency management automatically. Generated code executes directly on the AMD Ryzen AI NPU. We demonstrate IRONSmith across ML designs of increasing complexity, from a single-tile vector passthrough to multi-tile matrix operations to a complete Multi-Layer Perceptron, all designed visually and successfully executed on the AMD Ryzen AI NPU. IRONSmith serves educators, students, ML researchers, and engineers by bridging the gap between ML knowledge and NPU programming expertise, widening access to hardware that is rapidly becoming standard across consumer and enterprise devices.
CommentsAccepted at FastML 2026
