AI 中文总结
研究多量子比特处理器中量子比特寿命短的问题，通过有限元模拟发现连通性会导致表面损耗增加，连接到两个和四个耦合器时表面损耗分别增加1.3倍和1.8倍，归因于多种因素，还得出设计低损耗处理器的指导原则。
AI 中文摘要
近期设计与制造的进展使孤立超导传输子量子比特的能量弛豫时间增加到数百微秒，部分超过500μs。但在多量子比特处理器中，量子比特嵌入连通的量子比特 - 耦合器晶格时，寿命常比孤立量子比特短得多。本文用有限元模拟研究量子比特嵌入倒装芯片量子比特 - 耦合器晶格时表面参与率及表面介电损耗如何变化。对比表明更高连通性会导致更大表面损耗，连接到两个和四个耦合器时表面损耗分别增加1.3倍和1.8倍。此变化归因于耦合爪边缘场增加、更大连通金属网络中场重新分布及与耦合器模式的杂化。还研究了连通性引起的表面损耗代价如何依赖于量子比特电极和耦合爪的几何设计参数，并得出设计低损耗多量子比特处理器的指导原则。
英文摘要
Recent advances in design and fabrication have increased the energy-relaxation times of isolated superconducting transmon qubits to the hundreds-of-microseconds regime, with reported values exceeding 500 $μ$s. However, the same progress has not automatically translated to multiqubit processors, where qubits are embedded in connected qubit-coupler lattices and often exhibit much shorter lifetimes than isolated qubits. To identify possible sources of this discrepancy, here we use finite-element simulation to investigate how surface participation ratios and the resulting surface dielectric loss change when a qubit is embedded in a flip-chip qubit-coupler lattice. Controlled comparisons show that higher connectivity can indeed lead to larger surface loss: in the simulated lattice, connecting a qubit to two and four couplers increases the surface loss by factors of 1.3 and 1.8, respectively. We attribute this change to the combined effects of added edge fields from coupling claws, field redistribution over the larger connected metal network, and hybridization with coupler modes. We further examine how this connectivity-induced surface-loss penalty depends on the geometric design parameters of both the qubit electrodes and the coupling claws, and derive guidelines for designing low-loss multiqubit processors.
